Maxim Integrated MAXQ Family - Manual (Page 84)

9-6
MAXQ Family User’s Guide
9.2.1 16-Bit Timer: Auto-Reload/Compare
The 16-bit auto-reload/compare mode for Timer 2 is in effect when the Timer 2 mode select bit (T2MD) is cleared and the capture/com-
pare function definition bits are both cleared (CCF[1:0] = 00b). The Timer 2 value is contained in the T2V register. The Timer 2 run con-
trol bit (TR2) starts and stops the 16-bit Timer. The input clock for 16-bit Timer 2 is defined as the system clock divided by the ratio
specified by the T2DIV[2:0] prescale bits. The Timer begins counting from the value contained in the T2L:T2H register pair until over-
flowing. When an overflow occurs, the reload value (T2RH:T2RL) is reloaded instead of the x0000h state. The Timer 2 overflow flag
(TF2) is set every time that an overflow condition (T2V = 0xFFFFh) is detected. If Timer 2 interrupts have been enabled (ET2 = 1), the
TF2 flag can generate an interrupt request. When operating in compare mode, the capture/compare registers (T2CH:T2CL) are com-
pared versus the Timer 2 value registers. Whenever a compare match occurs, the capture/compare status flag (TCC2) is set. If Timer
2 interrupts have been enabled (ET2 = 1), this event is capable of generating an interrupt request. If the capture/compare register is
set to a value outside the Timer 2 counting range, a compare match is not signaled and the TCC2 flag is not set. Internally, a Timer 2
output clock is generated, which toggles on the cycle following any compare match or overflow, unless the compare match value has
been set equal to the overflow condition, in which case, only one toggle will occur. This clock may be sourced by certain peripherals
and/or may be output on one or more pins as permitted by the microcontroller.
9.2.1.1 Output Enable (PWM Out)
The Output Enable bits (T2OE[1:0]) enable the Timer 2 output clock to be presented on the pins associated with the respective bits. If
Timer 2 has a single I/O pin, the T2OE[0] bit is associated with the T2P pin and the T2OE[1] bit is not implemented (as it would serve
no purpose).
9.2.1.2 Polarity Control
The Polarity Control bits (T2POL[1:0]) can be used to modify (invert) the enabled clock outputs to the pin(s). The enabled clock outputs
(defined by T2OE[1:0]) will toggle on each compare match or overflow. The T2POL[1:0] bits are logically XORed with the Timer 2 out-
put signal, therefore setting a given T2POL[x] bit will result in a high starting state. The T2POL[n] bit can be changed at any time, how-
ever the assigned T2POL[n] state will take effect on the external pin only when the corresponding T2OE[n] bit is changed from 0 to 1.
When generating PWM output, please note that changing the compare match register can result in a perceived duty cycle inversion if a
compare match is missed or multiple compare matches occur during the reload to overflow counting.
9.2.1.3 Gated
To use the T2P pin as a timer-input clock gate, the T2OE[0] bit must be cleared to 0 and the G2EN bit must be set to 1. When T2OE[0]
= 1, the G2EN bit setting has no effect. When T2OE[0] is cleared to 0, the respective polarity control bit is used to modify the polarity
of the input signal to the Timer. In the gated mode, the Timer 2 input clock is gated anytime that the external signal matches the state
of the T2POL[0] bit. This means that the default clock gating condition for the T2P pin is logic low (since T2POL[0] = 0 default). Setting
T2POL[0] = 1 results in the Timer 2 input clock being gated when the T2P pin is high. Note if multiple pins are allocated for Timer 2
(i.e., T2P, T2PB), the primary pin can be used for clock gating, while the secondary pin can be used to output the gated PWM output
signal (if T2OE[1] = 1).
9.2.1.4 Single Shot (and Gating)
When operating in 16-bit compare mode, the single-shot is used to automate the generation of single pulses under software control or
in response to an external signal (single-shot gated). To generate single-shot output pulses solely under software control, the G2EN bit
should be cleared to 0, the output enables and polarity controls should be configured as desired, and the single-shot bit should be set
to 1. Writing the single-shot bit effectively overrides the TR2 = 0 condition until Timer 2 overflow/reload occurs. The single-shot bit is
automatically cleared once the overflow/reload occurs.
Writing SS2 and TR2 = 1 at the same time still causes the SS2 bit to stay in effect until an overflow/reload occurs; however, since TR2
was also written to 1, the specified PWM output continues even after SS2 becomes clear.
If two pins are available for the Timer 2 implementation, an additional mode is supported: single-shot gated. Single-shot gated requires
that the T2P pin be used as an input (T2OE[0] = 0). It also requires that G2EN = 1, thus differentiating it from the software controlled
single-shot mode on the second output pin. If G2EN is enabled and SS2 is written to 1, the gating condition must first be removed for
the single-shot enabled output to occur on the pin. When the clock gate is removed, the single-shot output occurs. Just as described,
the SS2 bit = 1 state remains in effect until overflow/reload. Note that this makes it possible for the single-shot to span multiple
gated/non-gated intervals. Once the SS2 = 1 conditions completes, if TR2 = 1, the gated PWM mode is in effect. Otherwise (TR2 = 0),
Timer 2 is stopped.
Maxim Integrated