Maxim Integrated MAXQ Family - Manual (Page 88)

9-10
MAXQ Family User’s Guide
9.3 Timer 2 Capture Application Examples
The following examples and accompanying figures (Figures 9-4 through 9-8) are used to demonstrate some of the Timer 2 functions.
All examples assume that pulse and/or period measurements do not exceed 2 16 input clocks and that capture register holds the
desired result.
9.3.1 Measure Low-Pulse Duration
To measure the duration of the first full low pulse seen on the T2P input pin, Timer 2 could be configured for a single shot capture, gat-
ing enabled for logic high, capture on the rising edge. The CPRL2 bit could optionally be set to generate a reload on the same rising
edge as that which the capture occurs if the preconfigured T2R value is expected to be needed next.
; ------------------ Reset State: T2R = T2V = T2C = 0000h ------------------------
MOVE T2CFG, #00000010b ; T2CI =0 (sysclk/N input)
; T2DIV[2:0] =000 (/1)
; T2MD =0 (16-bit)
; CCF[1:0] =01 (rising edge)
; C/T2 =0 (timer/capture)
MOVE T2CNA, #10100111b ; ET2 =1 (enable Timer 2 ints)
; T2OE[0] =0 (input)
; T2POL[0] =1 (gating level = ‘1’)
; TR2L:TR2 =00 (don’t start timer)
; CPRL2 =1 (reload on capture edge)
; SS2 =1 (single-shot mode)
; G2EN =1 (gating enabled)
; ------------------ TCC2 Interrupt : DURATION = T2C
T2P PIN
CODE EXECUTION:
POINT A
CODE EXECUTION:
POINT B
1A 2A
1B 2B 3B
EVENTS:
1A: GATING CONDITION REMOVED; SINGLE-SHOT CAPTURE CYCLE BEGINS.
2A: RISING EDGE CAUSES CAPTURE/RELOAD; SINGLE-SHOT CAPTURE CYCLE ENDS; DURATION = T2C.
1B: RISING EDGE CAUSES CAPTURE/RELOAD; SINGLE-SHOT CAPTURE CYCLE BEGINS, TIMER CLOCK GATED SINCE T2P PIN = 1.
2B: GATING CONDITION REMOVED; TIMER RUNS.
3B: RISING EDGE CAUSES CAPTURE/RELOAD; SINGLE-SHOT CAPTURE CYCLE ENDS; DURATION = T2C.
Figure 9-4. Timer 2 Application Example—Measure Low Pulse Width
Maxim Integrated