Maxim Integrated MAXQ Family - Manual (Page 135)

13.4 1-Wire Bus Master Commands
The 1-Wire Bus Master can generate special commands on the 1-Wire bus in addition to transmitting and receiving data. The com-
mands are generated via the setting of a corresponding bit in the Command Register (A[2:0] = 000b), which is documented below.
These operational modes are defined in the Book of iButton Standards.
13.4.1 1-Wire Command Register (OWA = 000b)
Bits 7 to 4: Reserved
Bit 3: 1-Wire Input (OW_IN). This bit always reflects the current logic state of the OW_IN line.
Bit 2: Force 1-Wire (FOW). Setting this bit to logic 1 forces OW line to a low value if the EN_FOW bit in the 1-Wire internal control reg-
ister is also set to logic 1. The FOW bit has no effect on the OW line when the EN_FOW bit is cleared to logic 0.
Bit 1: Search ROM Accelerator (SRA). Setting this bit to logic 1 places the Bus Master into Search ROM Accelerator mode to expe-
dite the Search ROM process and prevent the CPU from having to perform single-bit manipulations of the bus during a Search ROM
operation. Note that the receive buffer must be empty before invoking SRA mode. This mode of operation is used to get either the
addresses of all devices connected to the 1-Wire bus or the serial number of one device and simultaneously address the device.
Clearing this bit to logic 0 disables the Search ROM accelerator.
Bit 0: 1-Wire Reset (1WR). Setting this bit to logic 1 causes a reset on the 1-Wire bus, which must precede any command given on
the bus. Setting this bit also automatically clears the SRA bit. The 1WR bit is automatically cleared as soon as the 1-Wire bus reset
completes. The Bus Master sets the presence-detect interrupt flag (PD) when the reset is completed and sufficient time for a 1-Wire
reset to occur has passed. The result of the 1-Wire reset is placed in the Interrupt Register bit PDR. If a presence-detect pulse was
received, PDR is cleared; otherwise, it is set. This bit is cleared to logic 0 when no reset action is required.
13.5 Search Operation Using Search ROM Accelerator
The 1-Wire Bus Master supports a Search ROM Accelerator Mode to expedite learning of ROM IDs for those devices connected to the bus.
The bus master must determine the ROM IDs of the slave devices on the 1-Wire bus before it can address each slave device individually.
The Search ROM command (F0h) is used by the Bus Master to signal external 1-Wire devices that a ROM ID search will be conduct-
ed. The Search ROM command can be issued immediately following a Reset sequence initiated by the master. Once the search ROM
command has been issued by the bus master, slave devices simultaneously transmit, bit-by-bit, their unique ROM IDs. There are three
1-Wire bus time slots associated with each ROM ID bit acquisition. These three time slots are as follows:
1) Read Time Slot 1: each slave transmits a single bit of its ROM ID (lsb first).
2) Read Time Slot 2: each slave transmits a complementary bit to that transmitted in 1.
3) Write Time Slot: bus master transmits discrepancy decision bit if needed.
The ROM ID acquisition and selection process listed starts with the least significant bit of each slave device. If the ROM ID bits match
for all currently selected slave devices, the two read time slots will reflect complementary data, and the bus master will not need to
deselect or remove any slave devices from the selection process. The bus master simply repeats the Read Time Slot 1 data as its Write
Time Slot data in the third time slot, and continues to the next higher ROM ID bit acquisition period. Since it is expected that all 1-Wire
devices have unique ROM IDs, the first two read time slots inevitably result in conflicting data being driven on the bus for at least one
bit position when multiple slaves are connected. When this occurs, the wired-AND line state yields a 0 for both read time slots. At this
point, the master has to send a bit value 1 or 0 to select the devices that remain in the search process. All deselected devices are idle
until they receive a Reset Pulse. Table 13-2 shows the four possible scenarios for slave ROM ID read time slots.
13-6
MAXQ Family User’s Guide
Bit # 7 6 5 4 3 2 1 0
Name — — — — OW_IN FOW SRA 1WR
Reset 0 0 0 0 s 0 0 0
Access r r r r r rw rw rw
r = read, w = write, s = special
Maxim Integrated