Maxim Integrated MAXQ Family - Manual (Page 24)

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Certain MAXQ devices may also incorporate brownout detection capability. For these devices, an on-chip precision reference and
comparator monitor the supply voltage V DD to ensure that it is within acceptable limits. If V DD is below the power-fail level, the power
monitor initiates a reset condition. This can occur either when the MAXQ is first powered up when the V DD supply is above the POR
voltage threshold, or when V DD drops out of tolerance from an acceptable level.
In either case, the reset condition is maintained until V DD rises above the reset level V RST . Once V DD > V RST , execution may resume
following any necessary clock warmup delay.
When the processor exits from the power-on/brownout reset state, the POR bit in the Watchdog Control Register (WDCN) is set to 1
and can only be cleared by software. The user software can examine the POR bit following a reset to determine whether the reset was
caused by a power-on reset or by another source.
2.9.1.2 External Reset
During normal operation, the MAXQ device is placed into external reset mode by holding the RST pin at logic 0 for at least four clock
cycles. If MAXQ device is in the low-power Stop mode (i.e., system clock is not active), the RST pin becomes an asynchronous source,
forcing the reset state immediately after being taken to logic 0. Once the MAXQ enters Reset mode, it remains in reset as long as the
RST pin is held at logic 0. After the RST pin returns to logic 1, the processor exits the reset state within four clock cycles and begins
program execution at address 8000h.
For many MAXQ devices, the RST pin is an output as well as an input. If a reset condition is caused by another source (such as a
brownout reset, watchdog, or internal reset), an output reset pulse is generated at the RST pin for as long as the MAXQ remains in
reset. If the RST pin is connected to an RC reset circuit or a similar circuit, it may not be able to drive the output reset signal. However,
if this occurs it does not affect the internal reset condition.
2.9.1.3 Watchdog Timer Reset
The watchdog timer is a programmable hardware timer that can be set to reset the processor in the case of a software lockup or other
unrecoverable error. Once the watchdog is enabled in this manner, the processor must reset the watchdog timer periodically to avoid
a reset. If the processor does not reset the watchdog timer before it elapses, the watchdog will initiate a reset state.
If the watchdog resets the processor, it remains in reset, and holds the RST pin low, for four clock cycles. Once the reset condition is
removed, the processor will begin executing program code at address 8000h. When a reset occurs due to a watchdog timeout, the
Watchdog Timer Reset flag in the WDCN register is set to 1 and can only be cleared by software. User software can examine this bit
following a reset to determine if that reset was caused by a watchdog timeout.
2.9.1.4 Internal System Reset
MAXQ devices may incorporate functions that logically warrant the ability to generate an internal system reset. This reset generation
capability is assessed by MAXQ function based upon its expected use. In-system programming is a prime example of functionality that
benefits by having the ability to reset the device. The exact in-system programming protocol is somewhat device and interface spe-
cific, however, it is expected that, upon completion of in-system programming, many users want the ability to reset the system. This
internal (software-triggered) reset generation capability is possible following in-system programming.
2.9.2 Power Management Mode
There are two major sources of power dissipation in CMOS circuitry. The first is static dissipation caused by continuous leakage cur-
rent. The second is dynamic dissipation caused by transient switching current required to charge and discharge load capacitors, as
well as short circuit current produced by momentary connections between V DD and ground during gate switching.
Usually, it is the dynamic switching power dissipation that dominates the total power consumption, and this power dissipation (P D ) for
a CMOS circuit can be calculated in terms of load capacitance (C L ), power-supply voltage (V DD ) and operating frequency (f) as:
P D = C L x V DD
2 x f
Capacitance and supply voltage are technology dependent and relatively fixed. However, the operating frequency determines the clock
rate, and the required clock rate may be different from application to application depending on the amount of processing power required.
If an external crystal or oscillator is being used, the operating frequency can be adjusted by changing external components. However,
it may be the case that a single application may require maximum processing power at some times and very little at others. Power
Management mode allows an application to reduce its clock frequency, and therefore its power consumption, under software control.
Power Management Mode is invoked by setting the PMME bit to 1. Once this bit has been set, one system clock cycle will occur every
256 oscillator cycles. All operations continue as normal in this mode, but at the reduced clock rate. Power Management Mode can be
deactivated by clearing the PMME bit to 0; the PMME bit will also be cleared automatically to 0 by any reset condition.
MAXQ Family User’s Guide
Maxim Integrated