Maxim Integrated MAXQ Family - Manual (Page 110)

Table 10-3. Example Baud-Clock Generator Settings (SMOD = 1)
10.3 Framing Error Detection
A framing error occurs when a valid stop bit is not detected. This results in the possible improper reception of the serial word. The
UART can detect a framing error and notify the software. Typical causes of framing errors are noise and contention. The Framing Error
condition is reported in the SCON register for the UART.
The Framing Error bit, FE, is located in SCON.7. Note that this bit normally serves as SM0 and is described as SM0/FE_0 in the regis-
ter description. Framing Error information is made accessible by the FEDE (Framing Error Detection Enable) bit located at SMD.0.
When FEDE is set to logic 1, the framing error information is shown in SM0/FE (SCON.7). When FEDE is set to logic 0, the SM0 func-
tion is accessible. The information for bits SM0 and FE is actually stored in different registers. Changing FEDE only modifies which reg-
ister is accessed, not the contents of either.
The FE bit is set to 1 when a framing error occurs. It must be cleared by software. Note that the FEDE state must be 1 while reading
or writing the FE bit. Also note that receiving a properly framed serial word does not clear the FE bit. This must be done in software.
10-9
MAXQ Family User’s Guide
0
15 0
PR
16
ADDITION
BAUD CLOCK OUTPUT =
CARRY OUT FROM
PHASE ACCUMULATOR [16]
0
PHASE ACCUMULATOR
Figure 10-5. Baud-Clock Generator
SYSTEM CLOCK FREQUENCY
(MHz)
BAUD RATE
(PR SETTING)
SYSTEM CLOCK FREQUENCY
(MHZ)
BAUD RATE
(PR SETTING)
10
115,200 (5E5F);
57,600 (2F30);
19,200 (0FBB);
9600 (07DD);
2400 (01FF)
3.579545
57,600 (83D2);
19,200 (2BF1);
9600 (15F8);
2400 (057E)
8
115,200 (75F7);
57,600 (3AFB);
19,200 (13A9);
9600 (09D5);
2400 (0275)
2.4576
57,600 (C000);
19,200 (4000);
9600 (2000);
2400 (0800)
3.6864
115,200 (FFFF);
57,600 (8000);
19,200 (2AAB);
9600 (1555);
2400 (0555)
1
19,200 (9D49);
9600 (4EA5);
2400 (13A9)
Maxim Integrated