Maxim Integrated MAXQ Family - Manual (Page 23)

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MAXQ Family User’s Guide
• if the system clock divide ratio is 2, the interrupt request is recognized after 2 system clock;
• if the system clock divide ratio is 4 or greater, the interrupt request is recognized after 1 system clock;
An interrupt request with a pulse width less than three undivided clock cycles is not recognized. Note that the granularity of interrupt
source is at module level. Synchronous interrupts and sampled asynchronous interrupts assigned to the same module product a sin-
gle interrupt to the interrupt handler.
External interrupts, when enabled, can be used as switchback sources from power management mode. There is no latency associat-
ed with the switchback because the circuit is being clocked by an undivided clock source versus the divide-by-256 system clock. For
the same reason, there is no latency for other switchback sources that do not qualify as interrupt sources.
2.8.4 Interrupt Prioritization by Software
All interrupt sources of the MAXQ microcontroller naturally have the same priority. However, when CPU operation vectors to the pro-
grammed Interrupt Vector address, the order in which potential interrupt sources are interrogated is left entirely up to the user, as this
often depends upon the system design and application requirements. The Interrupt Mask system register provides the ability to know-
ingly block interrupts from modules considered to be of lesser priority and manually re-enable the interrupt servicing by the CPU (by set-
ting INS = 0). Using this procedure, a given interrupt service routine can continue executing, only to be interrupted by higher priority
interrupts. An example demonstrating this software prioritization is provided in the Handling Interrupts section of Section 3: Programming.
2.8.5 Interrupt Exception Window
An interrupt exception window is a noninterruptable execution cycle. During this cycle, the interrupt handler does not respond to any inter-
rupt requests. All interrupts that would normally be serviced during an interrupt exception window are delayed until the next execution cycle.
Interrupt exception windows are used when two or more instructions must be executed consecutively without any delays in between.
Currently, there is a single condition in the MAXQ microcontroller that causes an interrupt exception window: activation of the prefix
(PFX) register.
When the prefix register is activated by writing a value to it, it retains that value only for the next clock cycle. For the prefix value to be
used properly by the next instruction, the instruction that sets the prefix value and the instruction that uses it must always be execut-
ed back to back. Therefore, writing to the PFX register causes an interrupt exception window on the next cycle. If an interrupt occurs
during an interrupt exception window, an additional latency of one cycle in the interrupt handling will be caused as the interrupt will
not be serviced until the next cycle.
2.9 Operating Modes
In addition to the standard program execution mode, there are three other operating modes for the MAXQ. During Reset Mode, the
processor is temporarily halted by an external or internal reset source. During Power Management Mode, the processor executes
instructions at a reduced clock rate to decrease power consumption. Stop Mode halts execution and all internal clocks to save power
until an external stimulus indicates that processing should be resumed.
2.9.1 Reset Mode
When the MAXQ microcontroller is in Reset Mode, no instruction execution or other system or peripheral operations occur, and all
input/output pins return to default states. Once the condition that caused the reset (whether internal or external) is removed, the proces-
sor begins executing code at address 8000h.
There are four different sources that can cause the MAXQ to enter Reset Mode:
• Power-On/Brownout Reset
• External Reset
• Watchdog Timer Reset
• Internal System Reset
2.9.1.1 Power-On/Brownout Reset
An on-chip power-on reset (POR) circuit is provided to ensure proper initialization on internal device states. The power-on reset circuit
provides a minimum power-on-reset delay sufficient to accomplish this initialization. For fast V DD supply rise times, the MAXQ device
will, at a minimum, be held in reset for the power-on reset delay when initially powered up. For slow V DD supply rise times, the MAXQ
device will be held in reset until V DD is above the power-on-reset voltage threshold. The minimum POR delay and POR voltage thresh-
old can differ depending upon MAXQ device. Refer to the device data sheet(s) for specifics.
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