Maxim Integrated MAXQ Family - Manual (Page 153)

15-2
MAXQ Family User’s Guide
SECTION 15: TEST ACCESS PORT (TAP)
The MAXQ microcontroller incorporates a Test Access Port (TAP) and TAP controller for communication with a host device across a
4-wire synchronous serial interface. The TAP can be used by MAXQ microcontrollers to support in-system programming and/or in-cir-
cuit debug. The TAP is compatible with the JTAG IEEE standard 1149, and is formed by four interface signals, as described in the fol-
lowing table. For detailed information on the TAP and TAP controller, refer to IEEE STD 1149.1 "IEEE Standard Test Access Port and
Boundary-Scan Architecture."
15.1 TAP Controller
The TAP controller is a synchronous state machine that responds to changes at the TMS and TCK signals. Based on its state transi-
tion, the controller provides the clock and control sequence for TAP operation. The performance of the TAP is dependent on the TCK
clock frequency. The maximum TCK clock frequency should be limited to 1/8 the system clock frequency. This section provides a brief
description of the state machine and its state transitions. The state diagram in Figure 15-1 summarizes the transitions caused by the
TMS signal sampling on the rising edge at TCK. The TMS signal value is presented adjacent to each state transition in the figure.
15.2 TAP State Control
The TAP provides an independent serial channel to communicate synchronously with the host system. The TAP state control is achieved
through host manipulation of the Test Mode Select (TMS) and Test Clock (TCK) signals. The TMS signal is sampled at the rising edge
of TCK and decoded by the TAP controller to control movement between the TAP states. The TDI input and TDO output are meaning-
ful once the TAP is in a serial shift state (i.e., Shift-IR or Shift-DR).
15.2.1 Test-Logic-Reset
On a power-on reset, the TAP controller is initialized to the Test-Logic-Reset state and the instruction register (IR2:0) is initialized to the
By-Pass instruction so that it does not affect normal system operation. No matter what the state of the controller, it enters Test-Logic-
Reset when TMS is held high for at least five rising edges of TCK. The controller remains in the Test-Logic-Reset state if TMS remains
high. An erroneous low signal on the TMS can cause the controller to move into the Run-Test-Idle state, but no disturbance is caused
to system operation if the TMS signal is returned and kept at the intended logic high for three rising edges of TCK since this returns
the controller to the Test-Logic-Reset state.
15.2.2 Run-Test-Idle
As illustrated in Figure15-1, the Run-Test-Idle state is simply an intermediate state for getting to one of the two state sequences in which
the controller performs meaningful operations:
• Controller state sequence (IR-Scan), or
• Data register state sequence (DR-Scan)
EXTERNAL PIN
SIGNAL
FUNCTION
TDO
(Test Data Output)
Serial-Data Output. This signal is used to serially transfer internal data to the external host. Data is transferred least significant bit
first. Data is driven out only on the falling edge of TCK, only during TAP Shift-IR or Shift-DR states and is otherwise inactive.
TDI
(Test Data Input)
Serial-Data Input. This signal is used to receive data serially transferred by the host. Data is received least significant bit first and
is sampled on the rising edge of TCK. TDI is weakly pulled high internally when TAP = 1.
TCK
(Test Clock Input)
Serial Shift Clock Provided by Host. When this signal is stopped at 0, storage elements in the TAP logic must retain their data
indefinitely. TCK is weakly pulled high internally when TAP = 1.
TMS
(Test Mode Select
Input)
Mode Select Input. This signal is sampled at the rising edge of TCK and controls movement between TAP states. TMS is weakly
pulled high internally when TAP = 1.
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