Maxim Integrated MAXQ Family - Manual (Page 43)

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MAXQ Family User’s Guide
If the timeout is reached without RWT being set, hardware will generate a Watchdog interrupt if the interrupt source has been enabled.
If no further action is taken to prevent a Watchdog reset, in the 512 system clock cycles following the timeout, hardware has the abili-
ty to reset the CPU if EWT = 1. When the reset occurs, the Watchdog Timer Reset Flag (WTRF = WDCN.2) will automatically be set to
indicate the cause of the reset, however software must clear this bit manually.
The Watchdog Interrupt is also available for applications that do not need a true Watchdog Reset but simply a very long timer. The
interrupt is enabled using the Enable Watchdog Timer Interrupt (EWDI = WDCN.6) bit. When the timeout occurs, the Watchdog Timer
will set the WDIF bit (WDCN.3), and an interrupt will occur if the interrupt global enable (IGE = IC.0) and system interrupt mask (IMS
= IMR.7) are set and the interrupt in service (INS) bit is clear. Note that WDIF is set 512 clocks before a potential Watchdog Reset. The
Watchdog Interrupt Flag will indicate the source of the interrupt, and must be cleared by software.
Using the Watchdog Interrupt during software development can allow the user to select ideal watchdog reset locations. Code is first
developed without enabling the Watchdog Interrupt or Reset functions. Once the program is complete, the Watchdog Interrupt func-
tion is enabled to identify the required locations in code to set the RWT (WDCN.0) bit. Incrementally adding instructions to reset the
Watchdog Timer prior to each address location (identified by the Watchdog Interrupt) will allow the code to eventually run without
receiving a Watchdog Interrupt. At this point the Watchdog Timer Reset can be enabled without the potential of generating unwanted
resets. At the same time the Watchdog Interrupt may also be disabled. Proper use of the Watchdog Interrupt with the Watchdog Reset
allows interrupt software to survey the system for errant conditions.
When using the Watchdog Timer as a system monitor, the Watchdog Reset function should be used. If the Interrupt function were used,
the purpose of the watchdog would be defeated. For example, assume the system is executing errant code prior to the Watchdog
Interrupt. The interrupt would temporarily force the system back into control by vectoring the CPU to the interrupt service routine.
Restarting the Watchdog and exiting by an RETI or RET, would return the processor to the lost position prior to the interrupt. By using
the Watchdog Reset function, the processor is restarted from the beginning of the program, and therefore placed into a known state.
The Watchdog timeout selection is made using bits WD1 (WDCN.5) and WD0 (WDCN.4). The Watchdog has four timeout selections
based on the system clock frequency as shown in the figure. Since the timeout is a function of the system clock, the actual timeout
interval is dependent on both the crystal frequency and the system clock mode selection. Shown below is a summary of the selectable
Watchdog timeout intervals for the various system clock modes and WD1:0 control bit settings. The Watchdog Reset, if enabled, is
always scheduled to occur 512 system clocks following the timeout. Watchdog generated resets will last for 4 system clock cycles.
SYSTEM CLOCK
MODE
TIME-OUT
SELECTOR
WD1
XTAL2
XTAL1
WD0
DIVIDE BY
2 12
DIVIDE BY
2 3
2 12 2 15 2 18 2 21
DIVIDE BY
2 3
WDIF
(WDCN.3)
WTRF
(WDCN.2)
WATCHDOG
INTERRUPT
EWT (WDCN.1)
(ENABLE WATCHDOG TIMER RESET)
EWDI (WDCN.6)
(ENABLE WATCHDOG INTERRUPT)
512 SYSCLK
DELAY
DIVIDE BY
2 3
RWT (WDCN.0)
(RESET WATCHDOG)
TIME-OUT
RESET MAXQ
Figure 3-1. Watchdog Timer Block Diagram
Maxim Integrated