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Table 3-5. system register bit map -20, Maxq family user’s guide, Table 3-5. system register bit map – Maxim Integrated MAXQ Family User Manual

Page 45

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3-20

MAXQ Family User’s Guide

BIT POSITION

REGISTER

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

AP

AP (4 bits)

APC

CLR

IDS

MOD2

MOD1

MOD0

PSF

Z

S

GPF1

GPF0

OV

C

E

IC

CGDS

INS

IGE

IMR

IMS

IM5

IM4

IM3

IM2

IM1

IM0

SC

TAP

CDA1

CDA0

UPA

ROD

PWL

IIR

IIS

II5

II4

II3

II2

II1

II0

CKCN

XT/RC

RGSL

RGMD

STOP

SWB

PMME

CD1

CD0

WDCN

POR

EWDI

WD1

WD0

WDIF

WTRF

EWT

RWT

A[0]

A[0] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[1]

A[1] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[2]

A[2] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[3]

A[3] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[4]

A[4] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[5]

A[5] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[6]

A[6] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[7]

A[7] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[8]

A[8] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[9]

A[9] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[10]

A[10] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[11]

A[11] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[12]

A[12] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[13]

A[13] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[14]

A[14] (MAXQ10: 8 bits; MAXQ20:16 bits)

A[15]

A[15] (MAXQ10: 8 bits; MAXQ20:16 bits)

PFX[n]

PFX[n] (16 bits)

IP

IP (16 bits)

SP

SP (4 bits)

IV

IV (16 bits)

LC[0]

LC[0] (16 bits)

LC[1]

LC[1] (16 bits)

OFFS

OFFS (8 bits)

DPC

WBS2

WBS1

WBS0

SDPS1 SDPS0

GR

GR (16 bits)

GRL

GRL (8 bits)

BP

BP (16 bits)

GRS

GRS (16 bits) = (GRL, GRH)

GRH

GRH (8 bits)

GRXL

GRXL (16 bits) = (GRL.7, 8bits): (GRL, 8bits)

FP

FP = BP[Offs] (16 bits)

DP[0]

DP[0] (16 bits)

DP[1]

DP[1] (16 bits)

Table 3-5. System Register Bit Map

Maxim Integrated