Maxim Integrated MAXQ Family - Manual (Page 161)

The host now can transmit and receive serial data through the 10-bit data shift register that exists between the TDI input and TDO out-
put during DR-Scan sequences. All background and debug mode communication (commands, data input/output, and status) occurs
via this serial channel. Each 10-bit exchange of data between the host and the MAXQ internal hardware is composed of two status bits
and a single byte of command or data. The 10-bit word is always transmitted least significant bit first with the format shown below.
The data byte portion of the 10-bit shift register is interfaced directly to the ICDB parallel register. The ICDB register functions as the hold-
ing data register for both transmit and receive operations. On the falling edge of TCK in the Update-DR state, the outgoing data is loaded
from the ICDB parallel register to the debug shift register and the incoming shift register data is latched in the ICDB parallel register.
16.1 Background Mode Operation
When the instruction register is loaded with the Debug instruction (IR2:0 = 010b), the host can communicate with the MAXQ micro-
controller in a background mode using TAP DR-Scan sequences without disturbing CPU operation. Note, however, that JTAG in-sys-
tem programming also requires use of the 10-bit debug shift register and, if enabled (SPE, PSS1:0 = 100b), takes precedence over
background mode communication. When operating in background mode, the status bits are always cleared to 00b (non-debug), which
indicates that the MAXQ microcontroller is ready to receive background mode commands.
The host can perform the following operations from background mode:
• read/write internal breakpoint registers (BP0-BP5)
• read/write internal in-circuit debug registers (ICDC, ICDF, ICDA, ICDD)
• monitor to determine when a breakpoint match has occurred
• directly invoke debug mode
16-3
MAXQ Family User’s Guide
MAXQ
9 0 9 0
x x TDI TDO
Host Command / Data Input MAXQ Data Output
s1:s0 Status/Condition
00
Non-Debug. Default condition,
Background mode, or debug
engine inactive.
01 Debug Idle. Debug engine is
ready to receive data from the
host (command, data).
10 Debug Busy. Debug engine is
busy without valid data (i.e. ROM
code execution, trace operations).
11
Debug Valid. Debug engine is
busy with valid data
Maxim Integrated