5 breakpoint 4 regist, 6 breakpoint 4 regist, 5 breakpoint 4 register (bp4) (rege = 0) -7 – Maxim Integrated MAXQ Family User Manual
Page 165: 6 breakpoint 4 register (bp4) (rege = 1) -7, Maxq family user’s guide
16.1.1.5 Breakpoint 4 Register (BP4) (REGE = 0)
Bits 15 to 0: Breakpoint 4 (BP4.[15:0]). This register is accessible only via background mode read/write commands.
When (REGE = 0): This register serves as one of the two data memory address breakpoints. When DME is set in background mode,
the debug engine will monitor the data memory address bus activity while the CPU is executing the user program. If an address match
is detected, a break occurs, allowing the debug engine to take over control of the CPU and enter debug mode.
16.1.1.6 Breakpoint 4 Register (BP4) (REGE = 1)
Bits 15 to 9: Reserved
Bits 8 to 0: Breakpoint 4 (BP4.[8:0]). This register is accessible only via background mode read/write commands.
When (REGE = 1): This register serves as one of the two register breakpoints. A break occurs when the destination register address
for the executed instruction matches with the specified module and index.
16-7
MAXQ Family User’s Guide
Bit #
15
14
13
12
11
10
9
8
Name
(REGE = 0)
BP4.15
BP4.14
BP4.13
BP4.12
BP4.11
BP4.10
BP4.9
BP4.8
Reset
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s*
Bit #
7
6
5
4
3
2
1
0
Name
(REGE = 0)
BP4.7
BP4.6
BP4.5
BP4.4
BP4.3
BP4.2
BP4.1
BP4.0
Reset
1
1
1
1
1
1
1
1
Access
s*
s*
s*
s*
s**
s**
s**
s**
s = special, * = register index within module {0-31), ** = module specifier 3:0 {0-15}
Bit #
15
14
13
12
11
10
9
8
Name
(REGE = 1)
—
—
—
—
—
—
—
BP4.8
Reset
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s*
Bit #
7
6
5
4
3
2
1
0
Name
(REGE = 1)
BP4.7
BP4.6
BP4.5
BP4.4
BP4.3
BP4.2
BP4.1
BP4.0
Reset
1
1
1
1
1
1
1
1
Access
s*
s*
s*
s*
s**
s**
s**
s**
s = special, * = register index within module {0-31), ** = module specifier 3:0 {0-15}
Maxim Integrated