Maxim Integrated MAXQ Family - Manual (Page 168)

16.2.1 Debug Mode Commands
The debug engine sets the data shift register status bits to 01b (debug-idle) to indicate that it is ready to accept debug commands
from the host.
The host can perform the following operations from debug mode:
• read register map
• read program stack
• read/write register
• read/write data memory
• single step of CPU (trace)
• return to background mode
• unlock password
The only operations directly controlled by the debug engine are single step and return. All other operations are assisted by debug ser-
vice routines contained in the Utility ROM. These operations require that multiple bytes be transmitted and/or received by the host,
however each operation always begins with host transmission of a command byte. This command byte is decoded by the debug
engine in order to determine the quantity, sequence, and destination for follow-on bytes received from the host. Even though there is
no timing window specified for receiving the complete command and follow-on data, the debug engine must receive the correct num-
ber of bytes for a particular command before executing that command. If command and follow-on data are transmitted out of byte order
or proper sequence, the only way to resolve this situation is to disable the debug engine by changing the instruction register (IR2:0)
and reloading the Debug instruction. Once the debug engine has received the proper number of command and follow-on bytes for a
given ROM assisted operation, it will respond with the following actions:
• update the Command bits (CMD3:0) in the ICDC register to reflect the host request,
• enable the ROM if it is not been enabled,
• force a jump to ROM address x8010h, and
• set the data shift register status bits to 10b (debug-busy)
The ROM code performs a read to the ICDC register CMD3:0 bits to determine its course of action. Some commands can be processed
by the ROM without receiving data from the host beyond the initially supplied follow-on bytes, while others (e.g., Unlock Password)
require additional data from the host. Some commands need only to provide an indication of completion to the host, while others (Read
register map) need to supply multiple bytes of output data. To accomplish data flow control between the host and ROM, the status bits
should be used by the host to assess when the ROM is ready for additional data and/or when the ROM is providing valid data output.
Internally, the ROM can ascertain when new data is available or when it may output the next data byte via the TXC flag. The TXC flag
is an important indicator between the debug engine and the Utility ROM debug routines. The Utility ROM firmware sets the TXC flag to
1 to indicate that valid data has been loaded to the ICDB register. The debug engine clears the TXC flag to 0 to indicate completion
of a data shift cycle, thus allowing the ROM to continue execution of a requested task that is still in progress. The Utility ROM signals
that it has completed a requested task by setting the ROM Operation Done (ROD) bit of the SC register to logic 1. The ROD bit is reset
by the debug engine when it recognizes the done condition.
Table 16-2 shows the debug mode commands supported by the MAXQ microcontroller. Note that background mode commands are
supported inside debug mode, however the documentation of these commands can be found in the Background mode section of the
document. Encodings not listed in this table are not supported in debug mode and are treated as no operations.
16-10
MAXQ Family User’s Guide
Maxim Integrated