Maxim Integrated MAXQ Family - Manual (Page 86)

9-8
MAXQ Family User’s Guide
9.2.3.1 Output Enable
For Timer 2 to serve as a counter, the T2P pin must be used as an input. Thus, when C/T2 = 1, the T2OE[0] bit is ignored. The T2OE[1]
bit can be used to output the generated waveform on T2PB resulting from compare match and overflow conditions for the counter.
When generating PWM output, please note that changing the compare match register can result in a perceived duty cycle inversion if a
compare match is missed or multiple compare matches occur during the reload to overflow counting.
9.2.3.2 Polarity Control
Only the T2POL[1] bit is meaningful. It can define the starting state of the T2PB pin when the T2PB output has been enabled. The
T2POL[1] bit can be changed at any time, however the assigned T2POL[1] state will take effect on the external pin only when the cor-
responding T2OE[1] bit is changed from 0 to 1.
9.2.3.3 Gating and Single Shot
Neither gating nor single-shot modes are supported when operating in 16-bit counter mode. The G2EN and SS2 bits should not be set
to 1 when operating in the counter mode (C/T2 = 1).
9.2.4 Dual 8-Bit Timers
The dual 8-bit timer mode of operation is initiated by setting the T2MD bit to logic 1. When T2MD = 1, each 16-bit register associated
with Timer 2 is split into separate upper and lower 8-bit registers to support dual 8-bit timers. Thus, the primary 8-bit timer is composed
of T2H (value), T2RH (reload), T2CH (capture/compare), and the secondary 8-bit timer is composed of T2L(value), T2RL(reload), and
T2CH (capture/compare). There is still a single internal Timer 2 input clock that can be sourced by either of these two 8-bit timers. In
the dual 8-bit mode of operation, both Timer 2 output clocks (from T2L and T2H) are available to internal peripherals as required by a
given product. The secondary 8-bit timer/counter has its own run control bit (TR2L) and interrupt flags (TF2L, TC2L).
9.2.4.1 Output Enable (PWM Out)
The output enable bits (T2OE[1:0]) enable the respective 8-bit Timer 2 outputs to be presented on the pins associated with the respec-
tive bits. The T2H timer output onto the T2P pin is controlled by the T2OE[0] bit, and the T2L timer output onto the T2PB pin is con-
trolled by the T2OE[1] bit. If Timer 2 has a single I/O pin, only the T2OE[0] bit is required as the secondary timer T2L cannot be out-
put to a pin and can only serve as an internal timer.
9.2.4.2 Polarity Control
The polarity control bits (T2POL[1:0]) can be used to modify (invert) the enabled clock outputs to the pin(s). The starting state of the
enabled clock outputs (defined by T2OE[1:0]) is the logic state of T2POL[1:0] and toggles on each compare match or overflow. When
generating PWM output, please note that changing the compare match register can result in a perceived duty cycle inversion if a com-
pare match is missed or multiple compare matches occur during the reload to overflow counting. The T2POL[1:0] bits are logically XOR
with the Timer 2 output signal, therefore setting a given T2POL[x] bit results in a high starting state. The T2POL[n] bit can be changed
any time, however the assigned T2POL[n] state will take effect on the external pin only when the corresponding T2OE[n] bit is changed
from 0 to 1. T2POL[1] is not required for a single pin Timer 2 implementation.
9.2.4.3 Gated
To use the T2P pin as a G2EN, the T2OE[0] bit must be cleared to 0 and the G2EN bit must be set to 1. When T2OE[0] = 1, the G2EN
bit setting has no effect. When T2OE[0] is cleared to 0, the respective polarity control bit is used to modify the polarity of the input sig-
nal to the Timer. In the gated mode, the input clock to T2H is gated any time the external signal matches the state of the T2POL[0] bit.
This means that the default clock gating condition is associated with the T2P pin being low (T2POL[0] = 0). Note that the secondary
8-bit timer, T2L, cannot be gated. Also, since the output enables T2OE[1:0] apply to each individual 8-bit timer, there is no gated PWM
mode available.
9.2.4.4 Single Shot
The single-shot bit and mode apply only to the primary 8-bit timer (T2H). The single-shot mode is used to automate the generation of
single pulses under software control. To generate single-shot output pulses under software control, the G2EN bit should be cleared to
0, the output enables and polarity controls should be configured as desired and the single-shot bit should be set to 1. Writing the sin-
gle-shot bit effectively overrides the TR2 = 0 condition until Timer 2 overflow/reload occurs. Writing SS2 and TR2 = 1 at the same time
still causes the SS2 bit to stay in effect until an overflow/reload occurs. However, the specified PWM output continues since TR2 was
also written to 1.
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