Maxim Integrated MAXQ Family - Manual (Page 117)

11.4.3 Write Collision While Busy
A write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY = 1). Since the shift register
is single buffered in the transmit direction, writes to SPIB are made directly into the shift register. Allowing the write to SPIB while anoth-
er transfer is in progress could easily corrupt the transmit/receive data. When such a write attempt is made, the current transfer con-
tinues undisturbed, the attempted write data is not transferred to the shift register, and the control unit sets the Write Collision flag
(SPICN.4: WCOL). Setting the WCOL bit to logic 1 causes an interrupt if SPI interrupt sources are enabled. Once set, the WCOL bit is
cleared only by software or a reset.
Normally, write collisions are associated solely with slave devices since they do not control initiation of transfers and do not have access
to as much information about the SPICK clock as the master. As a master, write collisions are completely avoidable, however, the con-
trol unit detects write collisions for both master and slave modes.
11.5 SPI Master Operation
The SPI module is placed in master mode by setting the Master Mode Enable (MSTM) bit in the SPI Control register to logic 1. Only an
SPI master device can initiate a data transfer. The master is responsible for manually selecting/deselecting the desired slave devices.
This can be done using a general-purpose output pin. Writing a data character to the SPI shift register (SPIB) while in master mode starts
a data transfer. The SPI master immediately shifts out the data serially on the MOSI pin, most significant bit first, while providing the ser-
ial clock on SPICK output. New data is simultaneously received on the MISO pin into the least significant bit of the shift register. The data
transfer format (clock polarity and phase), character length, and baud rate are configurable as described earlier in the section. During
the transfer, the SPI Transfer Busy (SPICN.7:STBY) flag is set to indicate that a transfer is in process. At the end of the transfer, the data
contained in the shift register is moved into the receive data buffer, the STBY bit is cleared by hardware, and the SPI Transfer Complete
flag (SPICN.6: SPIC) is set. Setting the SPIC bit generates an interrupt request if SPI interrupt sources are enabled (ESPII = 1).
11.6 SPI Slave Operation
The SPI module operates in slave mode when the MSTM bit is cleared to logic 0. In slave mode, the SPI is dependent on the SPICK
sourced from the master to control the data transfer. The SPICK input frequency should be no greater than the system clock of the
slave device frequency divided by 8.
The Slave Select SSEL input must be externally asserted by a master before data exchange can take place. SSEL must be low before
data transaction begins and must remain low for the duration of the transaction. If data is to be transmitted by the slave device, it must
be written to its shift register before the beginning of a transfer cycle, otherwise the character already in the shift register will be trans-
ferred. The slave device considers a transfer to begin with the first clock edge or the falling edge of the SSEL, dependent on the data
transfer format.
The SPI slave receives data from the external master MOSI pin, most significant bit first, while simultaneously transferring the contents
of its shift register to the master on the MISO pin, also most significant bit first. Data received from the external master replaces data
in the internal shift register until the transfer completes. Just like in the master mode of operation, received data is loaded into the read
buffer and the SPI Transfer Complete flag is set at the end of transfer. The setting of the Transfer Complete flag generates an interrupt
request if enabled.
When SSEL is not asserted, the slave device ignores the SPICK clock and the shift register is disabled. Under this condition, the device
is basically idle, no data is shifted out from the shift register, and no data is sampled from the MOSI pin. The MISO pin is placed in an
input mode and is weakly pulled high to allow other devices on the bus to drive the bus. Deassertion of the SSEL signal by the mas-
ter during a transfer (before a full character, as defined by CHR, is received) aborts the current transfer. When the transfer is aborted,
no data is loaded into the read buffer, the SPIC flag is not set, and the slave logic and bit counter are reset.
In slave mode, the Clock Divider Ratio bits (CKR7:0) have no function since an external master supplies the serial clock. The transfer
format (CKPOL, CKPHA settings) and the character length selection (CHR) for the slave device, however, should match the master for
a proper communication.
11-5
MAXQ Family User’s Guide
Maxim Integrated