3 rtc seconds low regis, 4 rtc sub-seconds regis, 3 rtc seconds low register (rtsl) -8 – Maxim Integrated MAXQ Family User Manual
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MAXQ Family User’s Guide
14.4.3 RTC Seconds Low Register (RTSL)
Bits 15 to 0: RTC Seconds Low (RTSL.[15:0]). This register contains the least significant bits for the 32-bit second counter. The RTC
is a ripple counter that consists of a cascaded 32-bit second counter (RTSH, RTSL) and an 8-bit sub-second counter (RTSS). This reg-
ister is write-accessible when RTCE = 0 and BUSY = 0, and should be read-only when RDY = 1.
14.4.4 RTC Sub-Seconds Register (RTSS)
Bits 7 to 0: RTC Sub-Seconds (RTSS.[7:0]). This ripple counter represents 1/256 second resolution for the RTC, and its content is
incremented with each 256Hz clock tick derived from the 32.768 kHz oscillator (or alternate clock source if ACS = 1). When the RTSS
counter rolls over, its output is used to drive the 32-bit seconds counter. This register is write-accessible when RTCE = 0 and BUSY =
0, and should be read-only when RDY = 1.
Bit #
15
14
13
12
11
10
9
8
Name
RTSL.15
RTSL.14
RTSL.13
RTSL.12
RTSL.11
RTSL.10
RTSL.9
RTSL.8
Power-On Reset
0
0
0
0
0
0
0
0
Reset
u
u
u
u
u
u
u
u
Access
s
s
s
s
s
s
s
s
Bit #
7
6
5
4
3
2
1
0
Name
RTSL.7
RTSL.6
RTSL.5
RTSL.4
RTSL.3
RTSL.2
RTSL.1
RTSL.0
Power-On Reset
0
0
0
0
0
0
0
0
Reset
u
u
u
u
u
u
u
u
Access
s
s
s
s
s
s
s
s
s = special, u = unaffected
Bit #
7
6
5
4
3
2
1
0
Name
RTSS.7
RTSS.6
RTSS.5
RTSS.4
RTSS.3
RTSS.2
RTSS.1
RTSS.0
Power-On Reset
0
0
0
0
0
0
0
0
Reset
u
u
u
u
u
u
u
u
Access
s
s
s
s
s
s
s
s
s = special, u = unaffected
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