Maxim Integrated MAXQ Family - Manual (Page 85)

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MAXQ Family User’s Guide
9.2.1.5 Capture/Reload Control
For the 16-bit compare operating mode, the CPRL2 bit is not used.
9.2.2 16-Bit Timer: Capture Mode
The 16-bit capture mode requires that some event trigger the capture. Normally this event is an external edge. The CCF[1:0] bits define
which edge(s) cause a capture to occur. If CCF[1:0] = 01b, a rising edge causes a capture. If CCF[1:0] = 10b, a falling edge causes
a capture. If CCF[1:0] = 11b, rising and falling edges both cause a capture to occur. The CPRL2 bit enables both capture and reload
to occur on the specified edge(s).
9.2.2.1 Output Enables
In 16-bit capture mode, the output enables are meaningless. No output waveform is allowed since the capture/compare registers are
being used for the purpose of capturing the Timer 2 value.
9.2.2.2 Polarity Control
The polarity control bits (T2POL[1:0]) have no specific meaning as related to the output function since there is no output function. The
T2POL[0] bit is used to establish the gating condition for the single-edge capture mode when gating is enabled (G2EN = 1). If cap-
ture and reload are defined (CPRL2 = 1 and CCF[1:0] = 11b) for both edges, theT2POL[0] bit can be used to specify which edge does
not have an associated edge reload when gating has also been enabled (G2EN bit = 1). When the SS2 bit is used to delay the timer
run (for both edge capture), the T2POL[0] bit also defines which edge starts/ends the single-shot process.
9.2.2.3 Edge Detection
Edge detection was previously described (CCF[1:0] controlled).
9.2.2.4 Gated
If gating is specified, it uses the T2POL[0] bit to define when the input clock to Timer 2 is gated (just as described for the compare mode).
This mode can easily be used to measure or incrementally capture high or low pulse durations. If a predefined high/low duration is
required to generate an interrupt, the gated compare mode can also be used. Note that if capture is defined for both rising and falling
edges, gating would serve no useful purpose as it would result in redundant capture data/interrupts. For this reason, when G2EN = 1
and CCF[1:0] = 11b, the T2POL[0] bit is used to specify which edge is a capture-only edge when CPRL2 = 1 (gating of the reload event).
9.2.2.5 Single Shot
The single-shot bit overrides the TR2 = 0 bit setting for a single edge-to-edge capture cycle (as defined by the CCF[1:0] bits). The sin-
gle-shot takes effect (starting the timer) only when the edge defined by CCF[1:0] is detected or the defined gating condition is removed.
While a capture and/or reload can occur on this starting edge, the interrupt flag is not set since a single-shot event has been request-
ed. When rising or falling edge capture is defined, the single-shot mode is useful for measuring single periods. If gating is also speci-
fied for the single shot, the high/low pulse widths are easily measured. If rising and falling edges are defined, the T2POL[0] bit desig-
nates which edge starts/ends the single-shot cycle, but the starting edge does not cause the interrupt flag to set. If G2EN = 1 for the
two-edge capture, the alternate edge (opposite of defined start/end edge can only be used for capture, not capture and reload). For
T2POL[0] = 1, the falling edge starts and stops the single shot. This is important for combined duty cycle and period measurement.
9.2.2.6 Capture and Reload
The CPRL2 bit enables both capture and reload on the specified edge(s). The only exception to this rule is when the G2EN bit is set
to logic 1. When G2EN is set to 1, a reload does not occur on the edge specified by T2POL[0]: when T2POL[0] = 0, the falling edge
does not cause a reload; if T2POL[0] = 1, the rising edge does not cause a reload.
9.2.3 16-Bit Counter
The 16-bit counter mode is enabled by setting the C/T2 bit to logic 1. When C/T2 = 1, rising, falling, or both rising and falling edges are
counted as determined by the CCF[1:0] bits. If CCF[1:0] = 00b, neither edge is defined as a counted edge, and the T2H:T2L counter
holds its count since no edge is defined as the counting edge. When an overflow occurs, the reload value (T2R) is reloaded instead of
the x0000h state. The Timer/Counter 2 overflow flag (TF2) is set every time that an overflow occurs. If Timer/Counter 2 interrupts have
been enabled (ET2 = 1), the TF2 flag can generate an interrupt request. In counter mode, the capture/compare register (T2C) is com-
pared versus the Timer/Counter 2 value register. Whenever a compare match occurs, the capture/compare status flag (TCC2) is set. If
Timer/Counter 2 interrupts have been enabled (ET2 = 1), this event can generate an interrupt request. If the capture/compare register
is set to a value outside the Timer 2 counting range, a compare match is not signaled and the TCC2 flag is not set.
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