Maxim Integrated MAXQ Family - Manual (Page 12)

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post increment/decrement source pointers by a MOVE instruction or pre increment/decrement destination pointers by a MOVE instruc-
tion. Using Data Pointer indirectly with "++" will automatically increase the content of the active Data Pointer by 1 immediately follow-
ing the execution of read data transfer (@DP[n]++) or immediately preceding the execution of a write operation (@++DP[n]). Using
Data Pointer indirectly with "--" will decrease the content of the active Data Pointer by 1 immediately following the execution of read
data transfer (@DP[n]--) or immediately preceding the execution of a write operation (@--DP[n]).
The Frame Pointer (BP[Offs]) is formed by 16-bit unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer Offset Register
(Offs). Frame Pointer can be used as a post increment/decrement source pointer by a MOVE instruction or as a pre increment/decrement
destination pointer. Using Frame Pointer indirectly with "++" (@BP[++Offs] for a write or @BP[Offs++] for a read) will automatically increase
the content of the Frame Pointer Offset by 1 immediately before or after the execution of data transfer depending upon whether it is used
as a destination or source pointer respectively. Using Frame Pointer indirectly with "--" (@BP[--Offs] for a write or @BP[Offs--] for a read)
will decrease the content of the Frame Pointer Offset by 1 immediately before/after execution of data transfer depending upon whether it
is used as a destination or source pointer respectively. Note that the increment/decrement function affects the content of the Offs register
only, while the contents of the BP register remain unaffected by the borrow/carry out from the Offs register.
A data memory cycle contains only one system clock period to support fast internal execution. This allows read or write operations on
SRAM to be completed in one clock cycle. Data memory mapping and access control are handled by the MMU. Read/write access to
the data memory can be in word or in byte.
2.3.4 Stack Memory
A 16-bit wide on-chip stack is provided by the MAXQ for storage of program return addresses and general-purpose use. The stack is
used automatically by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced; it can
also be used explicitly to store and retrieve data by using the @SP- - source, @++SP destination, or the PUSH, POP, and POPI instruc-
tions. The POPI instruction acts identically to the POP instruction except that it additionally clears the INS bit.
The width of the stack is 16 bits to accommodate the instruction pointer size. The stack depth may vary between product implemen-
tations. As the stack pointer register SP is used to hold the index of the top of the stack, the maximum size of the stack allowed for a
MAXQ product is defined by the number of bits defined in the SP register (e.g., 3 bits for stack depth of 8, 4 bits for stack depth of 16).
On reset, the stack pointer SP initializes to the top of the stack (e.g. 07h for an 8-word stack, 0Fh for a 16-word stack). The CALL, PUSH,
and interrupt vectoring operations increment SP and then store a value at @SP. The RET, RETI, POP, and POPI operations retrieve the
value at @SP and then decrement SP.
As with the other RAM-based modules, the stack memory is initialized to indeterminate values upon reset or power-up. Stack memory
is dedicated for stack operations only and cannot be accessed through program or data address spaces.
2.4 Pseudo-Von Neumann Memory Mapping
The MAXQ supports a pseudo-Von Neumann memory structure that can merge program and data into a linear memory map. This is
accomplished by mapping the data memory into the program space or mapping program memory segment into the data space.
Program memory from x0000h to x7FFFh is the normal user code segment, followed by the utility ROM segment. The uppermost part
of the 64kWord memory is the logical area for data memory when accessed as a code segment.
The program memory is logically divided into four program pages:
• P0 contains the lower 16kWords,
• P1 contains the second 16kWords,
• P2 contains the third 16kWords, and
• P3 contains the fourth 16kWords.
By default, P2 and P3 are not accessible for program execution until they are explicitly activated by the user software. The Upper
Program Access (UPA) bit must be set to logic 1 to activate P2 and P3. Once UPA is set, P2 and P3 will occupy the upper half of the
64kWord program space. In this configuration (UPA = 1), the utility ROM cannot be accessed at program memory and the physical
data memory cannot be accessed logically in program space.
The logical mapping of physical program memory page(s) into data space depends upon two factors: physical memory currently in
use for program execution; and word/byte data memory access selection. If execution is from the utility ROM, physical program mem-
ory page(s) can logically be mapped to the upper half of data memory space. If logical data memory is used for execution, physical
program memory page(s) can logically be mapped to the lower half of data memory space. If byte access mode is selected, only one
MAXQ Family User’s Guide
Maxim Integrated