Maxim Integrated MAXQ Family - Manual (Page 21)

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MAXQ Family User’s Guide
2.8 Interrupts
The MAXQ provides a single, programmable interrupt vector (IV) that can be used to handle internal and external interrupts. Interrupts
can be generated from system level sources (e.g., watchdog timer) or by sources associated with the peripheral modules included in
the specific MAXQ microcontroller. Only one interrupt can be handled at a time, and all interrupts naturally have the same priority. A
programmable interrupt mask register allows software-controlled prioritization and nesting of high-priority interrupts.
2.8.1 Servicing Interrupts
For the MAXQ to service an interrupt, interrupts must be enabled globally, modularly, and locally. The Interrupt Global Enable (IGE) bit
located in the Interrupt Control (IC) register acts as a global interrupt mask. This bit defaults to 0, and it must be set to 1 before any
interrupt takes place.
The local interrupt-enable bit for a particular source is in one of the peripheral registers associated with that peripheral module, or in a
system register for any system interrupt source. Between the global and local enables are intermediate per-module and system interrupt
mask bits. These mask bits reside in the Interrupt Mask system register. By implementing intermediate per-module masking capability
in a single register, interrupt sources spanning multiple modules can be selectively enabled/disabled in a single instruction. This pro-
motes a simple, fast, and user-definable interrupt prioritization scheme. The interrupt source-enable hierarchy is illustrated in Figure 2-10.
When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level.
Interrupt flags must be cleared within the user interrupt routine to avoid repeated interrupts from the same source.
Since all interrupts vector to the address contained in the Interrupt Vector (IV) register, the Interrupt Identification Register (IIR) may be
used by the interrupt service routine to determine the module source of an interrupt. The IIR contains a bit flag for each peripheral mod-
ule and one flag associated with all system interrupts; if the bit for a module is set, then an interrupt is pending that was initiated by
that module. If a module is capable of generating interrupts for different reasons, then peripheral register bits inside the module pro-
vide a means to differentiate among interrupt sources.
The Interrupt Vector (IV) register provides the location of the interrupt service routine. It may be set to any location within program mem-
ory. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user program must deter-
mine whether a jump to 0000h came from a reset or interrupt source.
2.8.2 Interrupt System Operation
The interrupt handler hardware responds to any interrupt event when it is enabled. An interrupt event occurs when an interrupt flag is
set. All interrupt requests are sampled at the rising edge of the clock and can be serviced by the processor one clock cycle later,
assuming the request does not hit the interrupt exception window. The one-cycle stall between detection and acknowledgement/ser-
vicing is due to the fact that the current instruction may also be accessing the stack. For this reason, the CPU must allow the current
instruction to complete before pushing the stack and vectoring to IV. If an interrupt exception window is generated by the currently exe-
cuting instruction, the following instruction must be executed, so the interrupt service routine will be delayed an additional cycle.
Interrupt operation in the MAXQ CPU is essentially a state machine generated long CALL instruction. When the interrupt handler ser-
vices an interrupt, it temporarily takes control of the CPU to perform the following sequence of actions:
1) The next instruction fetch from program memory is cancelled.
2) The return address is pushed on to the stack.
3) The INS bit is set to 1 to prevent recursive interrupt calls.
4) The instruction pointer is set to the location of the interrupt service routine (contained in the Interrupt Vector register).
5) The CPU begins executing the interrupt service routine.
Once the interrupt service routine completes, it should use the RETI instruction to return to the main program. Execution of RETI
involves the following sequence of actions:
1) The return address is popped off the stack.
2) The INS bit is cleared to 0 to re-enable interrupt handling.
3) The instruction pointer is set to the return address that was popped off the stack.
4) The CPU continues execution of the main program.
Pending interrupt requests will not interrupt an RETI instruction; a new interrupt will be serviced after first being acknowledged in the
execution cycle which follows the RETI instruction and then after the standard one stall cycle of interrupt latency. This means there will
be at least two cycles between back-to-back interrupts.
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