Maxim Integrated MAXQ Family - Manual (Page 103)

10-2
MAXQ Family User’s Guide
SECTION 10: SERIAL I/O MODULE
The Serial I/O Module provides the MAXQ access to a universal asynchronous receiver/transmitter (UART) for serial communication
with framing error detection.
10.1 UART Modes
The UART supports four basic modes of operation, and is capable of both synchronous and asynchronous modes, with different pro-
tocols and baud rates. In the synchronous mode, the microcontroller supplies the clock and communication takes place in a half-
duplex manner, while the asynchronous mode supports full-duplex operation. Table 10-1 shows the four serial operating modes.
The UART has a control register (SCON) and a transmit/receive buffer register (SBUF). Transmit or receive buffer access depends upon
whether SBUF is used contextually as a source or destination. When SBUF is used as a source (read operation), the receive buffer will
be accessed. When SBUF is used as a destination (write operation), the transmit buffer is accessed. The UART receiver incorporates
a holding buffer so that it may receive an incoming word before software has read the previous one.
Please note that there is no single register bit that explicitly enables the UART for transmission. This means that the port pin(s) asso-
ciated with UART transmission (i.e., TXD, and RXD for mode 0) will be controlled by the PDx and POx port control register bits when
the UART is not actively transmitting a character.
Table 10-1. UART Mode Summary
10.1.1 UART Mode 0
This mode is used to communicate in synchronous, half-duplex format with devices that accept the MAXQ microcontroller as a mas-
ter. Figure 10-1 shows a functional block diagram and basic timing of this mode. As can be seen, there is one bidirectional data line
(RXD) and one shift clock line (TXD) used for communication. Mode 0 requires that the MAXQ microcontroller be the master since it
generates the serial shift clock for data transfers that occur in either direction.
The RXD signal is used for both transmission and reception. Data bits enter and exit LSb first. TXD provides the shift clock. The baud
rate is equal to the shift clock frequency. When not using Power Management Mode, the baud rate in Mode 0 is equivalent to the sys-
tem clock divided by either 12 or 4, as selected by SM2 bit (SCON.5) for the UART.
The UART begins transmitting when any instruction writes to SBUF. The internal shift register then begins to shift data out. The clock
is activated and transfers data until the 8-bit value is complete. Data is presented just prior to the falling edge of the shift clock (TXD)
so that an external device can latch the data using the rising edge.
The UART begins to receive data when the REN bit in the SCON register (SCON.4) is set to logic 1 and the RI bit (SCON.0) is set to
logic 0. This condition tells the UART that there is data to be shifted in. The shift clock (TXD) activates, and the UART latches incom-
ing data on the rising edge. The external device should therefore present data on the falling edge. This process continues until 8 bits
have been received. The RI bit is automatically set to logic 1 immediately following the last rising edge of the shift clock on TXD. This
causes reception to stop until the SBUF has been read and the RI bit cleared. When RI is cleared, another byte can be shifted in.
MODE
SYNCHRONOUS/
ASYNCHRONOUS
BAUD CLOCK* DATA BITS START/STOP 9TH BIT FUNCTION
0 Synchronous 4 or 12 clocks 8 None None
1 Asynchronous Baud Clock Generator 8 1 start, 1 stop None
2 Asynchronous 32 or 64 clocks 9 1 start, 1 stop 0, 1, parity
3 Asynchronous Baud Clock Generator 9 1 start, 1 stop 0, 1, parity
*Use of any system clock-divide modes or power management mode affects the baud clock.
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