1 breakpoint registers, 1 breakpoint 0 regist, 2 breakpoint 1 regist – Maxim Integrated MAXQ Family User Manual
Page 163: 1 breakpoint registers -5, 1 breakpoint 0 register (bp0) -5, 2 breakpoint 1 register (bp1) -5, Maxq family user’s guide
16.1.1 Breakpoint Registers
The MAXQ microcontroller incorporates six breakpoint registers (BP0-BP5) that are configurable by the host for establishing different
types of breakpoint mechanisms. The first four breakpoint registers (BP0-BP3) are 16-bit registers that are configurable as program
memory address breakpoints. When enabled, the debug engine will force a break when a match between the breakpoint register and
the program memory execution address occurs. The final two 16-bit breakpoint registers (BP4, BP5) are configurable in one of two
possible capacities. They may be configured as data memory address breakpoints or may be configured to support register access
breakpoints. In either case, if breakpoints are enabled and the defined breakpoint match occurs, the debug engine will generate a
break condition. The six breakpoint registers are documented below.
16.1.1.1 Breakpoint 0 Register (BP0)
Bits 15 to 0: Breakpoint 0 (BP0.[15:0]). This register is accessible only via background mode read/write commands. Breakpoint reg-
isters BP0, BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the debug
engine monitors the program-address bus activity while the CPU is executing the user program. If an address match is detected, a
break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
16.1.1.2 Breakpoint 1 Register (BP1)
Bits 15 to 0: Breakpoint 1 (BP1.[15:0]). This register is accessible only via background mode read/write commands. Breakpoint reg-
isters BP0, BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the debug
engine monitors the program-address bus activity while the CPU is executing the user program. If an address match is detected, a
break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
16-5
MAXQ Family User’s Guide
Bit #
15
14
13
12
11
10
9
8
Name
BP0.15
BP0.14
BP0.13
BP0.12
BP0.11
BP0.10
BP0.9
BP0.8
Reset
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
Bit #
7
6
5
4
3
2
1
0
Name
BP0.7
BP0.6
BP0.5
BP0.4
BP0.3
BP0.2
BP0.1
BP0.0
Reset
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
S
s = special
Bit #
15
14
13
12
11
10
9
8
Name
BP1.15
BP1.14
BP1.13
BP1.12
BP1.11
BP1.10
BP1.9
BP1.8
Reset
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
Bit #
7
6
5
4
3
2
1
0
Name
BP1.7
BP1.6
BP1.5
BP1.4
BP1.3
BP1.2
BP1.1
BP1.0
Reset
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
S
s = special
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