Maxim Integrated MAXQ Family - Manual (Page 25)

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MAXQ Family User’s Guide
The PMME bit may not be set to 1 if any potential switchback source is active. Attempts to set the PMME bit under these conditions
result in a no-op.
2.9.2.1 Switchback
When Power Management Mode is active, the MAXQ operates at a reduced clock rate. Although execution continues as normal,
peripherals that base their timing on the system clock such as the UART module and the SPI module may be unable to operate nor-
mally or at a high enough speed for proper application response. Additionally, interrupt latency is greatly increased.
The Switchback feature is used to allow a processor running under Power Management Mode to switch back to normal mode quickly
under certain conditions that require rapid response. Switchback is enabled by setting the SWB bit to 1. If Switchback is enabled, a
processor running under Power Management Mode automatically clears the PMME bit to 0 and returns to normal mode when any of
the following conditions occur:
• An external interrupt condition occurs on an INTx pin and the corresponding external interrupt is enabled.
• An active-low transition occurs on the UART serial receive-input line (modes 1, 2, and 3) and data reception is enabled.
• The SBUF register is written to send an outgoing byte through the UART and transmission is enabled.
• The SPIB register is written in master mode (STBY = 1) to send an outgoing character through the SPI module and transmission is enabled.
• The SPI module’s SSEL signal is asserted in slave mode.
• Time-of-Day and Subsecond interval alarms from the RTC when enabled.
• Active debug mode is entered either by break point match or issuance of the 'Debug' command from background mode.
2.9.3 Stop Mode
When the MAXQ is in Stop Mode, the CPU system clock is stopped, and all processing activity is halted. All on-chip peripherals requir-
ing the system clock are also stopped. Power consumption in Stop Mode is at the lowest possible level and is basically limited to sta-
tic leakage current.
Stop Mode is entered by setting the STOP bit to 1. The processor enters Stop Mode immediately once the instruction that sets the STOP
bit is executed. The MAXQ exits Stop Mode when any of the following conditions occur:
• An external interrupt condition occurs on one of the INTx pins and the corresponding external interrupt is enabled. After the inter-
rupt returns, execution resumes after the stop point.
• An external reset signal is applied to the RST pin. After the reset signal is removed, execution resumes at 8000h as it would after any
reset state.
In some MAXQ devices, the brownout voltage detection circuitry can be disabled during Stop Mode, so a power-fail condition does
not cause a reset as it would under normal conditions. Once the processor exits Stop Mode, it resumes execution as follows:
• If the RGSL bit is set to 0, the clock source selected by the XT/RC bit is enabled so that it may warm up/stabilize. During the warmup
period, the internal ring oscillator may be used for execution. The clock source switches from the ring oscillator to the XT/RC source
automatically once the warmup completes. The RGMD bit can be read by the processor to determine when the switch from the ring
oscillator to the XT/RC source has occurred.
• If the RGSL bit is set to 1, the internal ring oscillator will be used to resume execution and the XT/RC selected clock source will remain
disabled.
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