4 timer 2 value register, 5 timer 2 value high reg, 6 timer 2 reload registe – Maxim Integrated MAXQ Family User Manual
Page 96: 4 timer 2 value register (t2v) -18, 5 timer 2 value high register (t2h) -18, 6 timer 2 reload register (t2r) -18, Maxq family user’s guide, 4 timer 2 value register (t2v), 5 timer 2 value high register (t2h), 6 timer 2 reload register (t2r)
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MAXQ Family User’s Guide
9.4.4 Timer 2 Value Register (T2V)
Bits 15 to 0: Timer 2 Value (T2V.[15:0]). The T2V register is a 16-bit register that holds the current Timer 2 value. When operating in
16-bit mode (T2MD = 0), the full 16 bits are read/write accessible. If the dual 8-bit mode of operation (T2MD = 1) is selected, the upper
byte of T2V is inaccessible. T2V reads while in the dual 8-bit mode will return 00h as the high byte and writes to the upper byte of T2V
will be blocked. A separate T2H register is provided to facilitate high byte access for dual 8-bit mode.
9.4.5 Timer 2 Value High Register (T2H)
Bits 7 to 0: Timer 2 Value High (T2H.[7:0]). This register is used to load and read the most significant 8-bit value in Timer 2.
9.4.6 Timer 2 Reload Register (T2R)
Bits 15 to 0: Timer 2 Reload (T2R.[15:0]). This 16-bit register holds the reload value for Timer 2. When operating in 16-bit mode
(T2MD = 0), the full 16 bits are read/write accessible. If the dual 8-bit mode of operation is selected, the upper byte of T2R is inac-
cessible. T2R reads while in the dual 8-bit mode will return 00h as the high byte and writes to the upper byte of T2R will be blocked.
A separate T2RH register is provided to facilitate high byte access for the dual 8-bit mode.
Bit #
15
14
13
12
11
10
9
8
Name
T2V.15
T2V.14
T2V.13
T2V.12
T2V.11
T2V.10
T2V.9
T2V.8
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
Bit #
7
6
5
4
3
2
1
0
Name
T2V.7
T2V.6
T2V.5
T2V.4
T2V.3
T2V.2
T2V.1
T2V.0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
r = read, w = write
Bit #
7
6
5
4
3
2
1
0
Name
T2H.7
T2H.6
T2H.5
T2H.4
T2H.3
T2H.2
T2H.1
T2H.0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
r = read, w = write
Bit #
15
14
13
12
11
10
9
8
Name
T2R.15
T2R.14
T2R.13
T2R.12
T2R.11
T2R.10
T2R.9
T2R.8
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
Bit #
7
6
5
4
3
2
1
0
Name
T2R.7
T2R.6
T2R.5
T2R.4
T2R.3
T2R.2
T2R.1
T2R.0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
r = read, w = write
Maxim Integrated