Avago Technologies LSI53C825AE User Manual
Avago Technologies Hardware
Table of contents
Document Outline
- LSI53C825A/825AE PCI to SCSI I/O Processor
- Chapter1 Introduction
- Chapter2 Functional Description
- 2.1 PCI Addressing
- 2.2 SCSI Functional Description
- 2.3 External Memory Interface
- 2.4 PCI Cache Mode
- 2.4.1 Load and Store Instructions
- 2.4.2 3.3 V/5 V PCI Interface
- 2.4.3 Additional Access to General Purpose Pins
- 2.4.4 JTAG Boundary Scan Testing
- 2.4.5 Big and Little Endian Support
- 2.4.6 Loopback Mode
- 2.4.7 Parity Options
- 2.4.8 DMA FIFO
- 2.4.9 SCSI Bus Interface
- 2.4.10 Select/Reselect During Selection/Reselection
- 2.4.11 Synchronous Operation
- 2.4.12 Achieving Optimal SCSI Send Rates
- 2.4.13 Interrupt Handling
- 2.4.14 Chained Block Moves
- 2.5 Power Management
- Chapter3 Signal Descriptions
- Figure3.1 LSI53C825A Pin Diagram
- Figure3.2 LSI53C825AJ Pin Diagram
- Table 3.1 LSI53C825A, LSI53C825AJ, LSI53C825AE, and LSI53C825AJE Power and Ground Pins
- Figure3.3 LSI53C825A Functional Signal Grouping
- 3.1 PCI Bus Interface Signals
- 3.2 MAD Bus Programming
- Chapter4 Registers
- 4.1 Configuration Registers
- 4.2 Operating Registers
- Table 4.2 LSI53C825A Register Map
- Table 4.3 Synchronous Clock Conversion Factor
- Table 4.4 Examples of Synchronous Transfer Periods and Rates for SCSI-1
- Table 4.5 Example Transfer Periods and Rates for Fast SCSI-2
- Table 4.6 Maximum Synchronous Offset
- Table 4.7 Timeout Periods
- Table 4.8 Timeout Periods, 50 MHz Clock
- Chapter5 SCSI SCRIPTS Instruction Set
- Chapter6 Specifications
- 6.1 DC Characteristics
- Table 6.1 Absolute Maximum Stress Ratings
- Table 6.2 Operating Conditions
- Table 6.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/
- Table 6.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
- Table 6.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS, BIG_LIT/
- Table 6.6 Capacitance
- Table 6.7 Output Signals—MAC/_TESTOUT, REQ/
- Table 6.8 Output Signals—IRQ/, SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/...
- Table 6.9 Output Signal—SERR/
- Table 6.10 Bidirectional Signals—AD[31:0], C_BE[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...
- Table 6.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4
- Table 6.12 Bidirectional Signals—MAD[7:0]
- Table 6.13 Input Signals—TDI, TMS, TCK (LSI53C825AJ only)
- Table 6.14 Output Signal—TDO (LSI53C825AJ only)
- 6.2 TolerANT Technology Electrical Characteristics
- 6.3 AC Characteristics
- 6.4 PCI and External Memory Interface Timing Diagrams
- 6.4.1 Target Timing
- 6.4.2 Initiator Timing
- 6.4.3 External Memory Timing
- Figure6.21 Read Cycle, Normal/Fast Memory (³ 64 Kbytes), Single Byte Access
- Figure6.22 Write Cycle, Normal/Fast Memory (³ 64 Kbytes), Single Byte Access
- Figure6.23 Read Cycle, Normal/Fast Memory (³ 64 Kbytes), Multiple Byte Access
- Figure6.24 Write Cycle, Normal/Fast Memory (³ 64 Kbytes), Multiple Byte Access
- Figure6.25 Read Cycle, Slow Memory (³ 64 Kbytes)
- Figure6.26 Write Cycle, Slow Memory (³ 64 Kbytes)
- Figure6.27 Read Cycle, Normal/Fast Memory (³ 64 Kbytes)
- Figure6.28 Write Cycle, Normal/Fast Memory (³ 64 Kbytes)
- Figure6.29 Read Cycle, Slow Memory (£ 64 Kbytes)
- Figure6.30 Write Cycle, Slow Memory (£ 64 Kbytes)
- 6.5 PCI and External Memory Interface Timing
- 6.6 SCSI Timing Diagrams
- Table 6.20 Initiator Asynchronous Send
- Figure6.31 Initiator Asynchronous Send
- Table 6.21 Initiator Asynchronous Receive
- Figure6.32 Initiator Asynchronous Receive
- Table 6.22 Target Asynchronous Send
- Figure6.33 Target Asynchronous Send
- Table 6.23 Target Asynchronous Receive
- Figure6.34 Target Asynchronous Receive
- Figure6.35 Initiator and Target Synchronous Transfers
- Table 6.24 SCSI-1 Transfers (SE 5.0 Mbytes)
- Table 6.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s)
- Table 6.26 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transf...
- Table 6.27 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfers...
- 6.7 Package Drawings
- 6.1 DC Characteristics
- AppendixA Register Summary
- AppendixB External Memory Interface Diagram Examples
- Index
- Customer Feedback