Avago Technologies LSI53C825AE - Manual (Page 17)

TolerANT
®
Technology 1-3
1.2.1 PCI Pad Power-up Sequence
This power-up sequence should be followed when separate power
supplies are being applied to the VDD-IO and VDD-CORE pins in a chip
testing environment. Following this recommended power-up sequence
helps prevent potential damage to these devices.
1.2.1.1 Description of the Issue
The Universal PCI pad input receiver in this cell library has all devices in
a common N well attached to the 5 V core VDD supply. The P channel
is powered from the VDD PCI supply.
In the event that the I/O VDD PCI supply goes high prior to the core VDD
supply, the parasitic diode between the P channel source and the N well
of the device can become forward biased. This creates an excessive
current flow between the two nodes, and it causes damage to the device.
1.2.1.2 Solution for the Issue
In most system applications and production environments, the two VDD
pins power-up simultaneously. The user should know of this potential
hazard if using separate power supplies in a testing environment.
Either power-up the Core and I/O VDD PCI simultaneously, or if this is
not possible, power-up the Core VDD before powering up the I/O VDD
PCI supply.
Note that a power-down situation can have the same effect. The I/O must
always power-down prior to the Core.
1.3 TolerANT
®
Technology
The LSI53C825A features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation drives the SCSI Request, Acknowledge, Data,
and Parity signals HIGH rather than passively pulled up by terminators.
Active negation is enabled by setting bit 7 in the
SCSI Test Three
(STEST3) register.