Avago Technologies LSI53C825AE User Manual
Page 160
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Registers
M/A
SCSI Phase Mismatch - Initiator Mode; SCSI
ATN Condition - Target Mode
7
In the initiator mode, this bit is set when the SCSI phase
asserted by the target and sampled during SREQ/ does
not match the expected phase in the
register. This expected phase is
automatically written by SCSI SCRIPTS. In the target
mode, this bit is set when the initiator asserts SATN/. See
the Disable Halt on Parity Error or SATN/ Condition bit in
the
register for more
information on when this status is actually raised.
CMP
Function Complete
6
Indicates full arbitration and selection sequence is
completed.
SEL
Selected
5
Indicates the LSI53C825A is selected by a SCSI initiator
device. Set the Enable Response to Selection bit in the
register for this to occur.
RSL
Reselected
4
Indicates the LSI53C825A is reselected by a SCSI target
device. Set the Enable Response to Reselection bit in the
register for this to occur.
SGE
SCSI Gross Error
3
The following conditions are considered SCSI Gross
Errors:
•
Data underflow – reading the SCSI FIFO when no
data is present.
•
Data overflow – writing to the SCSI FIFO while it is
full.
•
Offset underflow – receiving a SACK/ pulse in the
target mode before the corresponding SREQ/ is sent.
•
Offset overflow – receiving a SREQ/ pulse in the
initiator mode, and exceeding the maximum offset
(defined by the MO[3:0] bits in the
register).
•
A phase change in the initiator mode, with an
outstanding SREQ/SACK offset.