7 opcode fetch burst capability, 3 external memory interface, Section 2.3, “external memory interface – Avago Technologies LSI53C825AE User Manual
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Functional Description
2.2.7 Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit in the
register (0x38) causes the LSI53C825A to burst in the first two longwords
of all instruction fetches. If the instruction is a memory-to-memory move,
the third longword is accessed in a separate ownership. If the instruction
is an indirect type, the additional longword is accessed in a subsequent
bus ownership. If the instruction is a table indirect Block Move, the chip
uses two accesses to obtain the four longwords required, in two bursts
of two longwords each.
Note:
This feature is only useful if prefetching is disabled.
2.3 External Memory Interface
The LSI53C825A supports up to one megabyte of external memory in
binary increments from 16 Kbytes, to allow the use of expansion ROM
for add-in PCI cards. The device also supports Flash ROM updates
through the add-in interface and the GPIO4 pin (used to control V
PP
, the
power supply for programming external memory). This interface is
designed for low speed operations such as downloading instruction code
from ROM; it is not intended for dynamic activities such as executing
instructions.
System requirements include the LSI53C825A, two or three external
8-bit address holding registers (HCT273 or HCT374), and the
appropriate memory device. The 4.7 k
Ω
pull-down resistors on the MAD
bus require HC or HCT external components to be used. If in-system
Flash ROM updates are required, a 7406 (high voltage open collector
inverter), an MTD4P05, and several passive components are also
needed. The memory size and speed is determined by pull-down
resistors on the 8-bit bidirectional memory bus at power-up. The
LSI53C825A senses this bus shortly after the release of the Reset signal
and configures the ROM Base Address register and the memory cycle
state machines for the appropriate conditions.
The external memory interface works with a variety of ROM sizes and
speeds. An example set of interface drawings is in