Avago Technologies LSI53C825AE User Manual
Page 68
2-44
Functional Description
transfer occurs similar to that of the regular block move instruction.
Whether the WSR bit is set or cleared, when a normal block move
instruction is executed, the contents of the
register are ignored and the transfer takes place normally. For “N”
consecutive wide data receive Block Move instructions, the 2nd through
the Nth Block Move instructions should be chained block moves.
For send data (Data-Out for initiator or Data-In for target), a chained
Block Move instruction indicates that if a partial transfer terminates the
chained block move instruction, the last low-order byte (the partial
memory transfer) should be stored in the lower byte of the
register and not sent across the SCSI bus. Without
the chained block move instruction, the last low-order byte would be sent
across the SCSI bus. The starting byte count represents data bytes
transferred from memory but not to the SCSI bus when a partial transfer
exists. For example, if the instruction is an Initiator chained Block Move
Data Out of five bytes (and WSS is not previously set), five bytes will be
transferred out of memory to the SCSI controller, four bytes are
transferred from the SCSI controller across the SCSI bus, and one byte
is temporarily stored in the lower byte of the
register waiting to be married with the first byte of the next block
move instruction. Regardless of whether a chained Block Move or normal
Block Move instruction is used, if the WSS bit is set at the start of a data
send command, the first byte of the data send command is assumed to
be the high-order byte and is “married” with the low-order byte stored in
the lower byte of the
register before the
two bytes are sent across the SCSI bus. For “N” consecutive wide data
send Block Move commands, the first through the (Nth – 1) Block Move
instructions should be Chained Block Moves.