Avago Technologies LSI53C825AE - Manual (Page 58)

2-34 Functional Description
2.4.11.2 SCSI Control Three (SCNTL3) Register, Bits [6:4]
The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI control logic.
The output from this divider controls the rate at which data can be
received; this rate must not exceed 50 MHz. The receive rate of
synchronous SCSI data is one-fourth of the SCF divider output. For
example, if SCLK is 40 MHz and the SCF value is set to divide by one,
then the maximum rate at which data can be received is 10 MHz
(40/(1*4) = 10).
2.4.11.3 SCSI Control Three (SCNTL3) Register, Bits [2:0]
The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the asynchronous SCSI core logic.
This divider must be set according to the input clock frequency in the
table.
2.4.11.4 SCSI Transfer (SXFER) Register, Bits [7:5]
The TP[2:0] divider bits determine the SCSI synchronous transfer period
when sending synchronous SCSI data in either initiator or target mode.
This value further divides the output from the SCF divider.
2.4.12 Achieving Optimal SCSI Send Rates
To achieve optimal synchronous SCSI send timings, the SCF divisor
value should be set HIGH, to divide the clock as much as possible before
presenting the clock to the TP divider bits in the
SCSI Transfer (SXFER)
register. The TP[2:0] divider value should be as low as possible. For
example, with a 40 MHz clock to achieve a 5 Mbytes/s send rate, the
SCF bits can be set to divide by 1 and the TP bits to divide by 8; or the
SCF bits can be set to divide by 2 and the TP bits set to divide by 2. Use
the second option to achieve optimal SCSI timings.
Figure 2.5 illustrates the clock division factors used in each register, and
the role of the register bits in determining the transfer rate.