Avago Technologies LSI53C825AE - Manual (Page 45)

PCI Cache Mode 2-21
2.4.7 Parity Options
The LSI53C825A implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures.
Table 2.3 defines the bits that
are involved in parity control and observation. Table 2.4 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the
SCSI Control Zero (SCNTL0) register. Table 2.5
describes the options available when a parity error occurs.
Table 2.3 Bits Used for Parity Control and Generation
BIt Name Location Description
Assert SATN/ on Parity
Errors SCSI Control
Zero (SCNTL0)
,
Bit 1
Causes the LSI53C825A to automatically assert SATN/
when it detects a parity error while operating as an
initiator.
Enable Parity Checking SCSI Control
Zero (SCNTL0)
,
Bit 3
Enables the LSI53C825A to check for parity errors.
The LSI53C825A checks for odd parity.
Assert Even SCSI Parity SCSI Control
One (SCNTL1)
,
Bit 2
Determines the SCSI parity sense generated by the
LSI53C825A to the SCSI bus.
Disable Halt on SATN/ or
a Parity Error (Target
Mode Only) SCSI Control
One (SCNTL1)
,
Bit 5
Causes the LSI53C825A not to halt operations when a
parity error is detected in target mode.
Enable Parity Error
Interrupt SCSI Interrupt
Enable Zero
(SIEN0)
, Bit 0
Determines whether the LSI53C825A will generate an
interrupt when it detects a SCSI parity error.
Parity Error SCSI Interrupt
Status Zero
(SIST0)
, Bit 0
This status bit is set whenever the LSI53C825A has
detected a parity error on the SCSI bus.