4 jtag boundary scan testing – Avago Technologies LSI53C825AE User Manual
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2-18
Functional Description
MAD7 pin and if GPIO0 and/or GPIO1 are sensed low after chip reset,
GPIO[1:0] access is disabled. If GPIO[1:0] access through configuration
space is enabled, the GPIO0 and GPIO1 pins cannot be controlled from
the
General Purpose Pin Control (GPCNTL)
and
registers, but are observable from the
register. When GPIO[1:0] access is enabled, the Serial
Interface Control register at configuration addresses 0x34–0x35 controls
the GPIO0 and GPIO1 pins. For more information on GPIO[1:0] access,
refer to the Serial Interface Control register description in
For more information on the GPIO pins, see
This does not apply to the LSI53C825AE.
Note:
The LSI Logic SDMS software controls the GPIO0 and
GPIO1 pins using the
and
registers.
Therefore, if using SDMS, do not connect a 4.7 k
Ω
resistor
between MAD7 and V
SS
.
2.4.4 JTAG Boundary Scan Testing
The LSI53C825AJ includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification, with one exception that
is discussed in this section. The device can accept all required boundary
scan instructions, as well as the optional CLAMP, HIGH-Z, and IDCODE
instructions.
The LSI53C825AJ uses an 8-bit instruction register to support all
boundary scan instructions. The data registers included in the device are
the Boundary Data register, the IDCODE register, and the Bypass
register. The device can handle a 10 MHz TCK frequency for TDO and
TDI.
Due to design constrains, the RST/ pin (System Reset) always
3-states the SCSI pins when it is asserted. This action cannot be
controlled by the boundary scan logic, and thus is not compliant with the
specification. There are two solutions that resolve this issue:
•
Use the RST/ pin as a boundary scan compliance pin. When the pin
is deasserted, the device is boundary scan compliant and when
asserted, the device is noncompliant. To maintain compliance, the
RST/ pin must be driven high.