Avago Technologies LSI53C825AE - Manual (Page 140)

4-52 Registers
Register: 0x18 (0x98)
Chip Test Zero (CTEST0)
Read/Write
FMT Byte Empty in DMA FIFO [7:0]
This was a general purpose read/write register in
previous LSI53C8XX family chips. Although it is still a
read/write register, LSI Logic reserves the right to use
these bits for future LSI53C8XX family enhancements.
Register: 0x19 (0x99)
Chip Test One (CTEST1)
Read Only
FMT[3:0] Byte Empty in DMA FIFO [7:4]
These bits identify the bottom bytes in the DMA FIFO that
are empty. Each bit corresponds to a byte lane in the
DMA FIFO. For example, if byte lane three is empty, then
FMT3 is set. Since the FMT flags indicate the status of
bytes at the bottom of the FIFO, if all FMT bits are set,
the DMA FIFO is empty.
FFL[3:0] Byte Full in DMA FIFO [3:0]
These status bits identify the top bytes in the DMA FIFO
that are full. Each bit corresponds to a byte lane in the
DMA FIFO. For example, if byte lane three is full then
FFL3 is set. Since the FFL flags indicate the status of
bytes at the top of the FIFO, if all FFL bits are set, the
DMA FIFO is full.
7 0
FMT
1 1 1 1 1 1 1 1
7 0
FMT[3:0] FFL[3:0]
1 1 1 1 0 0 0 0