Avago Technologies LSI53C825AE - Manual (Page 21)

LSI53C825A Benefits Summary 1-7
1.4.5 Flexibility
The LSI53C825A contains these flexibility features:
•
High level programming interface (SCSI SCRIPTS)
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Programs local memory bus Flash memory
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Big/little endian support
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Selectable 88-byte or 536-byte DMA FIFO for backward compatibility
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Tailored SCSI sequences execute from main system RAM or internal
SCRIPTS RAM
•
Flexible programming interface to tune I/O performance or to adapt
to unique SCSI devices
•
Support for changes in the logical I/O interface definition
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Low level access to all registers and all SCSI bus signals
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Fetch, Master, and Memory Access control pins
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Separate SCSI and system clocks
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Selectable IRQ pins disable bit
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32 additional scratch pad registers
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Ability to route system clock to SCSI clock
1.4.6 Reliability
The LSI53C825A contains these reliability features:
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2 kV ESD protection on SCSI signals
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Typical 300 mV SCSI bus hysteresis
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Protection against bus reflections due to impedance mismatches
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Controlled bus assertion times (reduces RFI, improves reliability, and
eases FCC certification)
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Latch-up protection greater than 150 mA
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Voltage feed-through protection (minimum leakage current through
SCSI pads)
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25% of pins are power and ground
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Power and ground isolation of I/O pads and internal chip logic