Avago Technologies LSI53C825AE User Manual
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Functional Description
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C825A asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.
2.4.13.2 Registers
The registers in the LSI53C825A that are used for detecting or defining
interrupts are the
,
SCSI Interrupt Status One (SIST1)
,
,
SCSI Interrupt Enable One (SIEN1)
,
, and
.
ISTAT – The
is the only register that can be
accessed as a slave during SCRIPTS operation, therefore it is the
register that is polled when polled interrupts are used. It is also the first
register that should be read when the IRQ/ pin has been asserted in
association with a hardware interrupt. The INTF (Interrupt-on-the-Fly) bit
should be the first interrupt serviced. It must be written to one to be
cleared. This interrupt must be cleared before servicing any other
interrupts. If the SIP bit in the ISTAT register is set, then a SCSI-type
interrupt has occurred and the
SCSI Interrupt Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
registers should be read. If the DIP
bit in the
register is set, then a DMA-type
interrupt has occurred and the
register should be
read. SCSI-type and DMA-type interrupts may occur simultaneously, so
in some cases both SIP and DIP may be set.
SIST0 and SIST1 – The
SCSI Interrupt Status Zero (SIST0)
and
registers contain the SCSI-type interrupt
bits. Reading these registers determines which condition or conditions
caused the SCSI-type interrupt, and clears that SCSI interrupt condition.
If the LSI53C825A is receiving data from the SCSI bus and a fatal
interrupt condition occurs, the chip attempts to send the contents of the
DMA FIFO to memory before generating the interrupt. If the LSI53C825A
is sending data to the SCSI bus and a fatal SCSI interrupt condition
occurs, data could be left in the DMA FIFO. Because of this the DMA
FIFO Empty (DFE) bit in
should be checked. If this