Avago Technologies LSI53C825AE - Manual (Page 134)

4-46 Registers
initiator or target mode. These bits are set when the
corresponding signal is active. They are useful when
operating in the low level mode.
Register: 0x0F (0x8F)
SCSI Status Two (SSTAT2)
Read Only
ILF1 SIDL Most Significant Byte Full 7
This bit is set when the most significant byte in the SCSI
Input Data Latch (SIDL) contains data. Data is transferred
from the SCSI bus to the SCSI Input Data Latch (SIDL)
register before being sent to the DMA FIFO and then to
the host bus. The
SCSI Input Data Latch (SIDL) register
contains SCSI data received asynchronously.
Synchronous data received does not flow through this
register.
ORF1 SODR Most Significant Byte Full 6
This bit is set when the most significant byte in the SCSI
Output Data register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR
register is used by the SCSI logic as a second storage
register when sending data synchronously. It is not
accessible to the user. This bit is used to determine how
many bytes reside in the chip when an error occurs.
OLF1 SODL Most Significant Byte Full 5
This bit is set when the most significant byte in the SCSI
Output Data Latch (SODL) contains data. The SCSI Out-
put Data Latch (SODL) register is the interface between
the DMA logic and the SCSI bus. In synchronous mode,
data is transferred from the host bus to the
SCSI Output
Data Latch (SODL) register, and then to the SCSI Output
Data register (SODR, a hidden buffer register which is
not accessible) before being sent to the SCSI bus. In
asynchronous mode, data is transferred from the host
bus to the
SCSI Output Data Latch (SODL) register, and
then to the SCSI bus. The SODR buffer register is not
7 6 5 4 3 2 1 0
ILF ORF1 OLF1 FF4 SPL1 DIFF LDSC SDP1
0 0 0 0 0 0 0 0