Avago Technologies LSI53C825AE - Manual (Page 251)

PCI and External Memory Interface Timing Diagrams 6-23
Figure 6.14 External Memory Write (Cont.)
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C825A)
STOP/
(Driven by LSI53C825A)
DEVSEL/
(Driven by LSI53C825A)
AD
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
LSI53C825A-Data)
LSI53C825A-Data)
MAD
(Driven by LSI53C825A)
MAS1/
(Driven by LSI53C825A)
MAS0/
(Driven by LSI53C825A)
MCE/
(Driven by LSI53C825A)
MOE/
(Driven by LSI53C825A)
MWE/
(Driven by LSI53C825A)
t
2
t
2
t
2
t
1
t
3
t
3
t
24
t
22
Data In
Byte Enable
In
Data Out
t
25
t
26
t
21
t
20
t
23
t
2
GPIO2_MAS2/
(Driven by LSI53C825A)
11 12 13 14 15 16 17 18 19 20 21