Avago Technologies LSI53C825AE User Manual
Page 163
Operating Registers
4-75
When performing consecutive 8-bit reads of the
,
SCSI Interrupt Status Zero (SIST0)
, and
registers (in any order), insert a delay equivalent to 12 clock
periods between the reads to ensure the interrupts clear properly. Also,
if reading the registers when both the
SIP and
DIP bits may not be set, read the
SCSI Interrupt Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
registers before the
register to avoid missing a SCSI interrupt. For more information
on interrupts refer to
Chapter 2, “Functional Description.”
M/A
Initiator Mode: Phase Mismatch; Target Mode:
SATN/ Active
7
In the initiator mode, this bit is set if the SCSI phase
asserted by the target does not match the instruction.
The phase is sampled when SREQ/ is asserted by the
target. In the target mode, this bit is set when the SATN/
signal is asserted by the initiator.
CMP
Function Complete
6
This bit is set when an arbitration only or full arbitration
sequence is completed.
SEL
Selected
5
This bit is set when the LSI53C825A is selected by
another SCSI device. The Enable Response to Selection
bit must be set in the
register (and
the
and
registers must hold the chip’s ID) for the
LSI53C825A to respond to selection attempts.
RSL
Reselected
4
This bit is set when the LSI53C825A is reselected by
another SCSI device. The Enable Response to
Reselection bit must be set in the
register (and the
and
registers must hold the
chip’s ID) for the LSI53C825A to respond to reselection
attempts.
SGE
SCSI Gross Error
3
This bit is set when the LSI53C825A encounters a SCSI
Gross Error Condition. The following conditions can result
in a SCSI Gross Error Condition:
•
Data Underflow – reading the SCSI FIFO when no
data is present.