Avago Technologies LSI53C825AE - Manual (Page 8)

viii Contents
2.4.1 Load and Store Instructions 2-17
2.4.2 3.3 V/5 V PCI Interface 2-17
2.4.3 Additional Access to General Purpose Pins 2-17
2.4.4 JTAG Boundary Scan Testing 2-18
2.4.5 Big and Little Endian Support 2-19
2.4.6 Loopback Mode 2-20
2.4.7 Parity Options 2-21
2.4.8 DMA FIFO 2-23
2.4.9 SCSI Bus Interface 2-27
2.4.10 Select/Reselect During Selection/Reselection 2-33
2.4.11 Synchronous Operation 2-33
2.4.12 Achieving Optimal SCSI Send Rates 2-34
2.4.13 Interrupt Handling 2-35
2.4.14 Chained Block Moves 2-42
2.5 Power Management 2-46
2.5.1 Power State D0 2-46
2.5.2 Power State D3 2-46
Chapter 3 Signal Descriptions
3.1 PCI Bus Interface Signals 3-6
3.1.1 System Signals 3-6
3.1.2 Address and Data Signals 3-7
3.1.3 Interface Control Signals 3-8
3.1.4 Arbitration Signals 3-9
3.1.5 Error Reporting Signals 3-9
3.1.6 SCSI Bus Interface Signals 3-10
3.1.7 Additional Interface Signals 3-11
3.1.8 External Memory Interface Signals 3-14
3.1.9 JTAG Signals 3-15
3.2 MAD Bus Programming 3-15
Chapter 4 Registers
4.1 Configuration Registers 4-1
4.2 Operating Registers 4-18