Avago Technologies LSI53C825AE - Manual (Page 271)

PCI and External Memory Interface Timing Diagrams 6-43
Figure 6.30 Write Cycle, Slow Memory (
≤
64 Kbytes)
MAD
(Driven by LSI53C825A)
MAS1/
(Driven by LSI53C825A)
MAS0/
(Driven by LSI53C825A)
MCE/
(Driven by LSI53C825A)
MOE/
(Driven by LSI53C825A)
MWE/
(Driven by LSI53C825A)
t
11
t
12
t
13
t
24s
t
25
t
20
t
23
t
22s
t
26
t
21
MAS2/
(Driven by LSI53C825A)
CLK
Lower
Address
Higher
Address
Valid Write Data