Avago Technologies LSI53C825AE - Manual (Page 203)

I/O Instruction 5-19
minimum of one Bus Free delay (400 ns), after the
LSI53C825A receives a Disconnect Message or a
Command Complete Message.
Wait Reselect Instruction
1. If the LSI53C825A is selected before being
reselected, it fetches the next instruction from the
address pointed to by the 32-bit jump address field
stored in the
DMA Next Address (DNAD) register.
Manually set the LSI53C825A to Target mode when it
is selected.
2. If the LSI53C825A is reselected, it fetches the next
instruction from the address pointed to by the DMA
SCRIPTS Pointer (DSP) register.
3. If the CPU sets the SIGP bit in the Interrupt Status
Zero (ISTAT0) register, the LSI53C825A aborts the
Wait Reselect instruction and fetches the next
instruction from the address pointed to by the 32-bit
jump address field stored in the
DMA Next Address
(DNAD) register.
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the
SCSI Output Control Latch
(SOCL) register are set. When the target bit is set, the
corresponding bit in the SCSI Control Zero (SCNTL0)
register is also set. When the carry bit is set, the
corresponding bit in the ALU is set.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the
SCSI Output Control Latch (SOCL) register. When the
target bit is cleared, the corresponding bit in the SCSI
Control Zero (SCNTL0) register is cleared. When the
carry bit is cleared, the corresponding bit in the ALU is
cleared.
RA Relative Addressing Mode 26
When this bit is set, the 24-bit signed value in the DMA
Next Address (DNAD) register is used as a relative
displacement from the current DMA SCRIPTS Pointer
(DSP) address. Use this bit only in conjunction with the