Avago Technologies LSI53C825AE User Manual
Page 196
5-12
SCSI SCRIPTS Instruction Set
5. If the SCSI phase bits do not match the value stored
in the
register, the
LSI53C825A generates a phase mismatch interrupt
and the instruction is not executed.
6. During a Message-Out phase, after the LSI53C825A
has performed a select with Attention (or SATN/ is
manually asserted with a Set ATN instruction), the
LSI53C825A deasserts SATN/ during the final
SREQ/SACK/ handshake.
7. When the LSI53C825A is performing a block move for
Message-In phase, it does not deassert the SACK/
signal for the last SREQ/SACK/ handshake. Clear the
SACK/ signal using the Clear SACK I/O instruction.
SCSIP[2:0]
SCSI Phase
[26:24]
This 3-bit field defines the SCSI information transfer
phase. When the LSI53C825A operates in Initiator mode,
these bits are compared with the latched SCSI phase bits
in the
register. When the
LSI53C825A operates in Target mode, it asserts the
phase defined in this field. The following table describes
the possible combinations and the corresponding SCSI
phase.
TC[23:0]
Transfer Counter
[23:0]
This 24-bit field specifies the number of data bytes to be
moved between the LSI53C825A and system memory.
The field is stored in the
register. When the LSI53C825A transfers data to/from
memory, the
register is
MSG C_D
I_O
SCSI Phase
0
0
0
Data-Out
0
0
1
Data-In
0
1
0
Command
0
1
1
Status
1
0
0
Reserved-Out
1
0
1
Reserved-In
1
1
0
Message-Out
1
1
1
Message-In