Avago Technologies LSI53C825AE - Manual (Page 264)

6-36 Specifications
Figure 6.24 Write Cycle, Normal/Fast Memory (
≥
64 Kbytes), Multiple Byte Access
MAD
(Driven by LSI53C825A)
GPIO2_MAS2/
(Driven by LSI53C825A)
MAS0/
(Driven by LSI53C825A)
MCE/
(Driven by LSI53C825A)
MOE/
(Driven by LSI53C825A)
MWE/
(Driven by LSI53C825A)
0 2 4 6 8 10 12 14
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C825A)
STOP/
(Driven by LSI53C825A)
DEVSEL/
(Driven by LSI53C825A)
AD
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
LSI53C825A-Data)
LSI53C825A-Data)
Byte Enable
Addr In
CMD
In
Upper
Address
Middle
Address
Lower
Address
Data In
MAS1/
(Driven by LSI53C825A)
1 3 5 7 9 11 13 15