Avago Technologies LSI53C825AE - Manual (Page 185)

LSI53C825A/825AE PCI to SCSI I/O Processor 5-1
Chapter 5
SCSI SCRIPTS
Instruction Set
After power-up and initialization of the LSI53C825A, the chip can be
operated in the low level register interface mode or in the high level SCSI
SCRIPTS mode.
Chapter 5 is divided into the following sections:
•
Section 5.1, “Low Level Register Interface Mode”
•
Section 5.2, “High Level SCSI SCRIPTS Mode”
•
Section 5.3, “Block Move Instructions”
•
Section 5.4, “I/O Instruction”
•
Section 5.5, “Read/Write Instructions”
•
Section 5.6, “Transfer Control Instructions”
•
Section 5.7, “Memory Move Instructions”
•
Section 5.8, “Load and Store Instructions”
5.1 Low Level Register Interface Mode
With the low level register interface mode, the user has access to the
DMA control logic and the SCSI bus control logic. An external processor
has access to the SCSI bus signals and the low level DMA signals, which
allows creation of complicated board level test algorithms. The low level
interface is useful for backward compatibility with SCSI devices that
require certain unique timings or bus sequences to operate properly.
Another feature allowed at the low level is loopback testing. In loopback
mode, the SCSI core can be directed to talk to the DMA core to test
internal data paths all the way out to the chip’s pins.