Avago Technologies LSI53C825AE - Manual (Page 243)

PCI and External Memory Interface Timing Diagrams 6-15
6.4.1 Target Timing
Figure 6.9 through Figure 6.14 describe Target timing.
Figure 6.9 PCI Configuration Register Read
Data Out
Byte Enable
t
2
In Out
t
1
t
2
t
1
t
3
t
2
t
1
t
1
t
2
t
2
t
3
t
3
t
2
t
1
t
3
t
2
t
1
CLK
(Driven by System)
FRAME/
(Driven by System)
C_BE/
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C825A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C825A)
STOP/
(Driven by LSI53C825A)
DEVSEL/
(Driven by LSI53C825A)
IDSEL
(Driven by Master)
CMD
Addr
In
AD/
(Driven by Master-Addr;
LSI53C825A-Data)