Avago Technologies LSI53C825AE - Manual (Page 78)

3-8 Signal Descriptions
3.1.3 Interface Control Signals
Table 3.4 describes the signals for the Interface Control Signals group:
Table 3.4 Interface Control Signals
Name Pin No. Type Description
FRAME/ 16 S/T/S Cycle Frame is driven by the current master to indicate the beginning
and duration of an access. FRAME/ is asserted to indicate a bus
transaction is beginning. While FRAME/ is asserted, data transfers
continue. When FRAME/ is deasserted, the transaction is in the final
data phase or the bus is idle.
TRDY/ 19 S/T/S Target Ready indicates the target agent’s (selected device’s) ability to
complete the current data phase of the transaction. TRDY/ is used with
IRDY/. A data phase is completed on any clock when both TRDY/ and
IRDY/ are sampled asserted. During a read, TRDY/ indicates that valid
data is present on AD[31:0]. During a write, it indicates the target is
prepared to accept data. Wait cycles are inserted until both IRDY/ and
TRDY/ are asserted together.
IRDY/ 17 S/T/S Initiator Ready indicates the initiating agent’s (bus master’s) ability to
complete the current data phase of the transaction. This signal is used
with TRDY/. A data phase is completed on any clock when both IRDY/
and TRDY/ are sampled asserted. During a write, IRDY/ indicates that
valid data is present on AD[31:0]. During a read, it indicates the master
is prepared to accept data. Wait cycles are inserted until both IRDY/ and
TRDY/ are asserted together.
STOP/ 22 S/T/S Stop indicates that the selected target is requesting the master to stop
the current transaction.
DEVSEL/ 20 S/T/S Device Select indicates that the driving device has decoded its address
as the target of the current access. As an input, it indicates to a master
whether any device on the bus has been selected.
IDSEL 2 I Initialization Device Select is used as a chip select in place of the
upper 24 address lines during configuration read and write transactions.