Avago Technologies LSI53C825AE - Manual (Page 131)

Operating Registers 4-43
Register: 0x0D (0x8D)
SCSI Status Zero (SSTAT0)
Read Only
ILF SIDL Least Significant Byte Full 7
This bit is set when the least significant byte in the SCSI
Input Data Latch (SIDL) register contains data. Data is
transferred from the SCSI bus to the SCSI Input Data
Latch (SIDL) register before being sent to the DMA FIFO
and then to the host bus. The SCSI Input Data Latch
(SIDL) register contains SCSI data received
asynchronously. Synchronous data received does not
flow through this register.
ORF SODR Least Significant Byte Full 6
This bit is set when the least significant byte in the SCSI
Output Data register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR is
used by the SCSI logic as a second storage register
when sending data synchronously. It is not readable or
writable by the user. It is possible to use this bit to
determine how many bytes reside in the chip when an
error occurs.
OLF SODL Least Significant Byte Full 5
This bit is set when the least significant byte in the SCSI
Output Data Latch (SODL) contains data. The SCSI Out-
put Data Latch (SODL) register is the interface between
the DMA logic and the SCSI bus. In synchronous mode,
data is transferred from the host bus to the
SCSI Output
Data Latch (SODL) register, and then to the SCSI Output
Data register (SODR, a hidden buffer register which is
not accessible) before being sent to the SCSI bus. In
asynchronous mode, data is transferred from the host
bus to the
SCSI Output Data Latch (SODL) register, and
then to the SCSI bus. The SODR buffer register is not
used for asynchronous transfers. It is possible to use this
bit to determine how many bytes reside in the chip when
an error occurs.
7 6 5 4 3 2 1 0
ILF ORF OLF AIP LOA WOA RST/ SDP0/
0 0 0 0 0 0 0 0