Avago Technologies LSI53C825AE - Manual (Page 81)

PCI Bus Interface Signals 3-11
3.1.7 Additional Interface Signals
Table 3.8 describes the signals for the Additional Interface Signals group:
RSTDIR 77 O Driver Enable Control for SCSI RST/ signal.
BSYDIR 78 O Driver Enable Control for SCSI BSY/ signal.
IGS 75 O Direction Control for initiator driver group.
TGS 73 O Direction Control for target driver group.
Table 3.7 SCSI Bus Interface Signals (Cont.)
Name Pin No. Type Description
Table 3.8 Additional Interface Signals
Name Pin No. Type Description
TESTIN (Not
available on
LSI53C825AJ) 57, NA I Test In. When this pin is driven LOW, the LSI53C825A connects
all inputs and outputs to an “AND tree.” The SCSI control
signals and data lines are not connected to the “AND tree.” The
output of the “AND tree” is connected to the Test Out pin. This
allows manufacturers to verify chip connectivity and determine
exactly which pins are not properly attached. When the TESTIN
pin is driven LOW, internal pull-ups are enabled on all input,
output, and bidirectional pins, all outputs and bidirectional
signals are 3-stated, and the MAC/_TESTOUT pin is enabled.
Connectivity can be tested by driving one of the LSI53C825A
pins LOW. The MAC/_TESTOUT pin should respond by also
driving LOW.
GPIO0_
FETCH/ 53/70/N5 I/O General Purpose I/O pin. Optionally, when driven LOW, this pin
indicates that the next bus request will be for an opcode fetch.
This pin powers up as a general purpose input.
This pin has two specific purposes in the LSI Logic SDMS
software. SDMS software uses it to toggle SCSI device LEDs,
turning on the LED whenever the LSI53C825A is on the SCSI
bus. SDMS software drives this pin LOW to turn on the LED, or
drives it HIGH to turn off the LED. This signal can also be used
as data I/O for serial EEPROM access. In this case it is used
with the GPIO0 pin, which serves as a clock, and the pin can
be controlled from PCI configuration register 0x35 or observed
from the
General Purpose (GPREG) register, at address 0x07.