Avago Technologies LSI53C825AE - Manual (Page 293)

Index IX-3
A
A[6:0] 5-26
abort operation (ABRT) 4-48
aborted (ABRT) 4-41
,
4-67
absolute maximum stress ratings 6-2
AC characteristics 6-11
active termination 2-29
adder sum output (ADDER) 4-70
address and data signals 3-7
always wide SCSI (AWS) 4-89
arbitration
arbitration signals 3-9
in progress (AIP) 4-44
mode bits 1 and 0 (ARB[1:0]) 4-20
priority encoder test (ART) 4-86
assert
even SCSI parity (force bad parity) (AESP) 4-24
SATN/ on parity error (AAP) 4-22
SCSI
ACK/ signal (ACK) 4-38
,
4-39
ATN/ signal (ATN) 4-38
,
4-39
BSY/ signal (BSY) 4-38
,
4-39
C_D/ signal (C_D) 4-38
,
4-40
data bus (ADB) 4-23
I_O/ signal (I/O) 4-38
,
4-40
MSG/ signal (MSG) 4-38
,
4-40
REQ/ signal (REQ) 4-38
,
4-39
RST/ signal (RST) 4-24
SEL/ signal (SEL) 4-38
,
4-39
B
base address register
one (BARO[31:0]) 4-9
one (BART[31:0]) 4-10
zero - I/O (BARZ[31:0]) 4-9
bidirectional 3-4
big and little endian support 2-19
block move instructions 5-6
bridge support extensions (BSE[7:0]) 4-17
burst
disable (BDIS) 4-57
length (BL[1:0]) 4-64
length bit 2 (BL2) 4-60
opcode fetch enable (BOF) 4-66
bus
fault (BF) 4-41
,
4-67
byte
count 5-41
empty in DMA FIFO (FMT) 4-52
full in DMA FIFO (FFL[3:0]) 4-52
offset counter (BO[7:0]) 4-56
C
cache line size
(CLS[7:0]) 4-8
enable (CLSE) 4-68
call instruction 5-30
cap_ID (CID[7:0]) 4-14
capabilities pointer (CP[7:0]) 4-12
carry test 5-34
chained block moves 2-42
SODL register 2-43
SWIDE register 2-43
wide SCSI receive bit 2-42
wide SCSI send bit 2-42
chained mode (CHM) 4-26
chip
revision level (V[3:0]) 4-54
test five (CTEST5) 4-59
test four (CTEST4) 4-57
test one (CTEST1) 4-52
test six (CTEST6) 4-60
test three (CTEST3) 4-54
test two (CTEST2) 4-53
test zero (CTEST0) 4-52
type (TYP[3:0]) 4-79
clear DMA FIFO (CLF) 4-55
clear instruction 5-16
,
5-19
clear SCSI FIFO (CSF) 4-91
clock
address incrementor (ADCK) 4-59
byte counter (BBCK) 4-59
conversion factor (CCF[2:0]) 4-29
compare
data 5-35
phase 5-35
configured
as I/O (CIO) 4-53
as memory (CM) 4-53
connected (CON) 4-24
,
4-50
D
data
(DATA[7:0]) 4-17
acknowledge status (DACK) 4-54
compare mask 5-36
compare value 5-36
request status (DREQ) 4-54
structure address (DSA) 4-48
transfer direction (DDIR) 4-53
data path 2-24
destination
address 5-26
I/O-memory enable (DIOM) 4-65
differential mode
DIFFSENS 3-12
direction control pins 3-10
operation 2-28
diffsens mismatch (DIFF) 4-47
DIFFSENS SCSI signal 6-3
direct 5-21
disable
halt on parity error or ATN (target only) (DHP) 4-24
single initiator response (DSI) 4-91
disconnect instruction 5-15
DMA
byte counter (DBC) 4-61
command (DCMD) 4-62
control (DCNTL) 4-68
direction (DDIR) 4-60
FIFO
(DF[7:0]) 4-60
(DFIFO) 4-56
byte offset counter, bits [9:8] (BO[9:8]) 4-60
empty (DFE) 4-40
size (DFS) 4-59
interrupt
enable (DIEN) 4-67