Avago Technologies LSI53C825AE - Manual (Page 257)

PCI and External Memory Interface Timing Diagrams 6-29
Figure 6.19 Burst Read (Cont.)
t
1
CMD
t
2
BE
Data In
Out In In Out In
BE
Addr
Out
CLK
GPIO0_FETCH/
(Driven by LSI53C825A)
GPIO1_MASTER/
(Driven by LSI53C825A)
REQ/
(Driven by LSI53C825A)
PAR
(Driven by LSI53C825A-
IRDY/
(Driven by LSI53C825A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
AD
(Driven by LSI53C825A-
C_BE/
(Driven by LSI53C825A)
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C825A)
Addr; Target-Data)
Addr; Target-Data)