Avago Technologies LSI53C825AE - Manual (Page 250)

6-22 Specifications
Figure 6.14 External Memory Write
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C825A)
STOP/
(Driven by LSI53C825A)
DEVSEL/
(Driven by LSI53C825A)
AD
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
1 2 3 4 5 6 7 8 9 10
LSI53C825A-Data)
Byte Enable
LSI53C825A-Data)
MAD
(Driven by LSI53C825A)
High Order
Address
Middle Order
Address
Low Order
Address
GPIO2_MAS2/
(Driven by LSI53C825A)
MAS1/
(Driven by LSI53C825A)
MAS0/
(Driven by LSI53C825A)
MCE/
(Driven by LSI53C825A)
MOE/
(Driven by LSI53C825A)
t
1
t
2
t
1
t
2
In
t
1
t
2
t
1
t
2
t
1
t
3
t
13
t
11
t
12
Data In
t
23
t
20
t
1
Addr
In
CMD
MWE/
(Driven by LSI53C825A)