Avago Technologies LSI53C825AE User Manual
Page 61
PCI Cache Mode
2-37
bit is clear, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO)
bits before continuing. The CLF bit is bit 2 in
.
The CSF bit is bit 1 in
.
DSTAT – The
register contains the DMA-type
interrupt bits. Reading this register determines which condition or
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DSTAT, DFE, is purely a status bit. It does not generate
an interrupt under any circumstances and will not be cleared when read.
DMA interrupts flush neither the DMA nor SCSI FIFOs before generating
the interrupt, so the DFE bit in the
register should
be checked after any DMA interrupt. If the DFE bit is cleared, then the
FIFOs must be cleared by setting the CLF (Clear DMA FIFO) and CSF
(Clear SCSI FIFO) bits, or flushed by setting the FLF (Flush DMA FIFO)
bit.
SIEN0 and SIEN1 – The
SCSI Interrupt Enable Zero (SIEN0)
and
registers are the interrupt enable registers
for the SCSI interrupts in
SCSI Interrupt Status Zero (SIST0)
and
DIEN – The
register is the interrupt enable
register for DMA interrupts in
.
DCNTL – When bit 1 in this register is set, the IRQ/ pin is not asserted
when an interrupt condition occurs. The interrupt is not lost or ignored,
but merely masked at the pin. Clearing this bit when an interrupt is
pending immediately causes the IRQ/ pin to assert. As with any register
other than
, this register cannot be accessed
except by a SCRIPTS instruction during SCRIPTS execution.
2.4.13.3 Fatal vs. Nonfatal Interrupts
A fatal interrupt, as the name implies, always causes SCRIPTS to stop
running. All nonfatal interrupts become fatal when they are enabled by
setting the appropriate interrupt enable bit. Interrupt masking will be
discussed in
All DMA interrupts (indicated
by the DIP bit in
and one or more bits in
being set) are fatal.